Programmable Interrupt Controller
15-20 Élan™SC520 Microcontroller User’s Manual
15.6 INITIALIZATION
The programmable interrupt controller responds only to system reset.
The Slave 1, Slave 2, and Master interrupt controllers are not affected by system reset.
The interrupt controller direct-mapped registers, once configured, retain their values during
a system reset. However, all other configuration registers default to their power-on reset
states when a system reset occurs. The interrupt router is reset, such that the interrupt
requests are gated off. This effectively disables all interrupt requests from reaching the CPU.
At system reset, the PIC is disabled.
1. Configure the Master, Slave 1, and Slave 2 controllers as described in “Configuration
Information” on page 15-16. Mask all interrupts.
2. Place an interrupt service routine at the locations corresponding to the interrupt priority
levels to be supported.
3. Enable the desired priority levels by mapping the interrupts sources to the interrupt levels
in the interrupt router and unmasking the interrupt in the corresponding interrupt
controllers. Set the IF bit in the CPU’s Flags register using the STI instruction. (NMIs
are disabled on system and soft reset and must be enabled via NMI_ENB bit before use).
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