AMD Elan SC520 - Test Access Port (TAP) Controller

Boundary Scan Test Interface
25-14 Élan™SC520 Microcontroller User’s Manual
value of the MINORSTEP field of the ÉlanSC520 Microcontroller Revision ID (REVID)
register (MMCR offset 00h).
Figure 25-3 Device Identification Register Format
25.4.3 Test Access Port (TAP) Controller
The test access port (TAP) controller is a synchronous, finite state-machine that controls
the sequence of operations of the test logic. The TAP controller changes state in response
to the rising edge of JTAG_TCK. It can be reset to the Test-Logic-Reset state either by
holding the JTAG_TRST
pin Low or by holding the JTAG_TMS pin High for five JTAG_TCK
periods.
The TAP controller state-machine is shown in Figure 25-4.
Part Number
Manufacturer Identity
31
1112
0
Bit Name Function
31–28 VERSION Value of the MINORSTEP field of the
ÉlanSC520 Microcontroller Revision
ID (REVID) register
27–0 Part Number and
Manufacturer Identity
Hardcoded to 0EFF003h
Version
28
27