PCI Bus Host Bridge
Élan™SC520 Microcontroller User’s Manual 9-27
9.5.5 Interrupts
The PCI host bridge has one maskable interrupt request signal and one NMI signal routed
to the ÉlanSC520 microcontroller’s interrupt controller. These interrupt signals are shared
by the arbiter, and PCI master and target controllers of the host bridge. Each interrupt
source (both master and target sources) can be individually programmed to generate a
maskable interrupt instead of a non-maskable interrupt request.
The following conditions can be programmed to generate an interrupt by the PCI host bridge
master
controller:
■ Detected parity error during a read cycle
■ Received parity during a write cycle or during the address phase of a read cycle
■ Retry time-out counter expired
■ Cycle was terminated with master abort
■ Cycle was terminated with target abort
■ System error (SERR) pin asserted by PCI bus device
When an interrupt is generated, the
address of the cycle
during which the interrupt condition
was detected is stored in the Host Bridge Master Interrupt Address (MSTINTADD) register
(MMCR offset 6Ch), and the
command
is stored in the Host Bridge Master Interrupt Status
(HBMSTIRQSTA) register (MMCR offset 68h). If multiple interrupt conditions are pending,
the registers store the information for the first interrupt condition only. If multiple interrupts
are pending, there is no indication to which interrupts the Master Interrupt Command
Identification (M_CMD_IRQ_ID) and Master Interrupt Address Identification
(M_AD_IRQ_ID) fields correspond. Status bits in the Status/Command (PCISTACMD)
register (PCI index 04h) are also set when error conditions are detected. These bits are
set whenever the error condition is detected, regardless of the interrupt enable bits.
The following conditions can be programmed to generate an interrupt by the host bridge
target
controller:
■ Detected parity error during a data phase of a write cycle
■ Detected parity error during an address phase
■ Delayed transaction time-out—2
15
clocks have expired without an external PCI master
retrying a delayed transaction
When an interrupt is generated, the
REQ/GNT number of the PCI bus master
that caused
the error is stored in the Host Bridge Target Interrupt Status (HBTGTIRQSTA) register
(MMCR offset 64h). If multiple interrupt conditions are pending, the Target Interrupt
Identification (T_IRQ_ID) field stores only the information for the first interrupt condition. If
multiple interrupts are pending, there is no indication to which interrupt the T_IRQ_ID field
corresponds. The appropriate status bits in the Status/Command (PCISTACMD) register
(PCI index 04h) are also set when error conditions are detected. These bits are set
whenever the error condition is detected, regardless of the interrupt enable bits.
See Chapter 15, “Programmable Interrupt Controller”, for further details on the
programming and routing of interrupt requests. See Chapter 8, “System Arbitration”, for
further details on arbitration.
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