AMD Elan SC520 - SDRAM Loading; Table 10-2 Estimated Capacitance (4-Bit SDRAM Devices); Table 10-3 Estimated Capacitance (8-Bit SDRAM Devices)

SDRAM Controller
10-8 Élan™SC520 Microcontroller User’s Manual
10.3.3 SDRAM Loading
Table 10-2 through Table 10-5 show estimated capacitances for the SDRAM devices that
the ÉlanSC520 microcontroller can support. (See Table 10-8 on page 10-13 for a listing of
the SDRAM devices supported by ÉlanSC520 microcontroller.) The tables are broken up
for SDRAM device data width for clarity. The purpose of these tables is to identify SDRAM
loading as it applies to various bank configurations. The ÉlanSC520 microcontroller
provides some flexibility in signal drive strength to allow the user to optimize performance,
depending on the SDRAM array configuration.
In the estimated capacitance tables, the input capacitance of SRASx
, SCASx, SWEx, MAx,
BAx, SDQMx, and SCSx
for a single device was assumed to be 5 pF. 4 pF was used for
the CLK signal. The MDx signals are assumed to be 6 pF. These tables do not account for
board trace capacitance. It is assumed in these tables that both pins provided for a control
signal, e.g., SRASA
–SRASB, SCASA–SCASB, and SWEA–SWEB are split across banks
evenly.
As can be seen in the tables, a 4-bank configuration of 16-bit devices has a loading of less
than 50 pF for any signal, but for a 4-bank configuration of 4-bit devices, the capacitance
of the interface increases. The ÉlanSC520 microcontroller provides programmable drive
strength buffers on all address, data, and control signals to support varying SDRAM device
loads. See “SDRAM Control Configuration” on page 10-18 for more details.
Notes:
Capacitive loads shown in the table above are derived from an estimated SDRAM pin capacitance
value of 5 pF for SRASx
, SCASx, SWEx, MAx, BAx, SDQMx, and SCSx; 4 pF for the CLK signal;
and 6 pF for the MDx signals, per device.
Notes:
Capacitive loads shown in the table above are derived from an estimated SDRAM pin capacitance
value of 5 pF for SRASx
, SCASx, SWEx, MAx, BAx, SDQMx, and SCSx; 4 pF for the CLK signal;
and 6 pF for the MDx signals, per device.
Table 10-2 Estimated Capacitance (4-Bit SDRAM Devices)
Number
of 32-Bit
Banks
CLK
Loading
(pF)
SRASx
Loading
(pF)
SCASx
Loading
(pF)
SCSx
Loading
(pF)
SWEx
Loading
(pF)
SDQMx
Loading
(pF)
MAx/BAx
Loading
(pF)
MDx
Loading
(pF)
1 32404040401040 6
2 64404040402080 12
3 96808040803012018
4 128 80 80 40 80 40 160 24
Table 10-3 Estimated Capacitance (8-Bit SDRAM Devices)
Number
of 32-Bit
Banks
CLK
Loading
(pF)
SRASx
Loading
(pF)
SCASx
Loading
(pF)
SCSx
Loading
(pF)
SWEx
Loading
(pF)
SDQMx
Loading
(pF)
MAx/BAx
Loading
(pF)
MDx
Loading
(pF)
1 16202020205 20 6
2 32202020201040 12
3 48404020401560 18
4 64404020402080 24