AMD Elan SC520 - Figure 7-1 Am5 X 86 CPU Block Diagram

Am5
x
86
®
CPU
7-2 Élan™SC520 Microcontroller User’s Manual
Figure 7-1 Am5
x
86® CPU Block Diagram
Central and
Protection
Test Unit
Control
ROM
Instruction
Decode
Barrel Shifter
ALU
Register File
Segmentation
Unit
Descriptor
Registers
Paging Unit
Translation
Look-Aside
Buffer
Limit and
Attribute
PLA
Cache Unit
Prefetcher
32-Byte
Code Queue
2 x 16 Bytes
Address
Drivers
Data Bus
Transceivers
Cache
Control
Linear Address Bus
32-Bit Data Bus
32-Bit Data Bus
32
24
32
20
2
32 32
32
128
Micro-instruction
Decoded Instruction Path
Code
Stream
Physical
Address
pcd, pwt
32
Base/
Index
Bus
Displacement Bus
Bus
a31-a2
be3-be0
d31-d0
64-Bit Interunit Transfer Bus
Am5
x
86® CPU
Boundary
Scan
Control
Clock
Core
Clock
Generator
Core
Clock
Floating
Point
Unit
FPU
Register
File
Bus Control
AMDebug™
100/133
Interface
Generation
Unit
JTAG_TRST
JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS
STOP/TX
BR/TC
CMDACK
TRIG/TRACE
ken, flush,
eads
, inv
16-Kbyte
Cache
Buffers
Control
Signals
Logic
Am5
x
86® CPU Bus
Élan™SC520 Microcontroller