AMD Elan SC520 - Configuration Base Address (CBAR) Register; I;O Space

System Address Mapping
4-10 Élan™SC520 Microcontroller User’s Manual
MMCR register space has a higher priority than the Programmable Address Region (PAR)
registers.
See Section 4.3.4.1 for details on programming the CBAR register.
Reading unimplemented registers in this 4-Kbyte region returns indeterminate data values.
Writing to unimplemented registers in this region has no effect.
4.3.3.5.1 Integrated Memory-Mapped Peripherals
The ÉlanSC520 microcontroller’s non-PC/AT integrated peripherals are located within the
MMCR region, instead of being I/O mapped as are the integrated PC/AT peripherals. The
peripherals located in the memory-mapped configuration region include:
■ Am5
x
86 CPU extension registers
■ SDRAM controller and SDRAM buffering
■ ROM controller
■ PCI host bridge
■ System arbitration
■ Memory and I/O space control
■ GP bus controller
■ PIO, pin multiplexing and clock control
■ Software timer
■ General-purpose timers 0, 1 and 2
■ Watchdog timer
■ Synchronous serial interface (SSI)
■ Feature enhancements to PC/AT-compatible peripherals
– Programmable interval timer (PIT) extension registers in the programmable input/
output (PIO) and programmable interrupt controller (PIC) blocks
– UART extensions
– Programmable interrupt controller (PIC) extensions
– Reset control
– GP-DMA controller extensions
4.3.4 I/O Space
The ÉlanSC520 microcontroller’s I/O space is partitioned into five regions:
■ Configuration Base Address (CBAR) register
■ PCI bus configuration space
■ External PCI bus I/O devices
■ Integrated PC/AT-compatible peripherals
■ External GP bus I/O devices
Figure 4-3 shows the system I/O address space map for the ÉlanSC520 microcontroller.
Each of the regions is described in the following sections.