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AMD Elan SC520 - Chapter 12 Rom;Flash Controller; Overview; Table 12-1 Rom;Flash Data Bus Connection Options

AMD Elan SC520
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Élan™SC520 Microcontroller Users Manual 12-1
CHAPTER
12
ROM/FLASH CONTROLLER
12.1 OVERVIEW
The ÉlanSC520 microcontroller includes an integrated ROM controller that provides a high
performance interface to ROMs, EPROMs, and Flash devices. Improved performance is
achieved by supporting a full 32-bit data path and advanced page-mode devices.
Note that in this document the term
ROM
is used interchangeably with Flash and EPROM
for simplicity. In addition, the term
ROM
is used to denote the entire bank of ROM devices
connected to a chip select, e.g., a 32-bit ROM can be implemented as four discrete 8-bit
ROM devices.
Features of the ROM controller include:
Support for a wide variety of industry standard ROMs, EPROMs, and Flash devices,
including advanced page-mode devices.
Three chip selects are provided. Each chip select supports up to 64 Mbytes.
One chip select is dedicated to booting.
The remaining two chip selects are optional and are multiplexed with GP bus chip
selects.
Programmable timing for both non-page-mode and page-mode devices is supported.
Programmable Address Region (PAR) register attributes provide code execution control,
cacheabilitity control, and write protection for Flash devices
The ÉlanSC520 microcontroller supports 8-bit, 16-bit, and 32-bit ROM configurations.
The GP address bus is always used for the ROM address, but the ROM data bus can
be connected to either the GP bus data bus or the SDRAM data bus.
For the boot device (BOOTCS), a set of configuration pins latched into the chip when
PWRGOOD is asserted is used to determine the width of the ROM array and which of
the two buses (GP bus or SDRAM interface) is used for the ROM data bus.
The remaining two optional chip selects are configured via configuration registers in
the ROM controller.
8-bit and 16-bit ROM configurations are supported when ROMs are connected to either
the GP bus or the SDRAM data bus. 32-bit ROM configurations are supported only when
ROMs are connected to the SDRAM data bus, as shown in Table 12-1.
Table 12-1 ROM/Flash Data Bus Connection Options
Data Bus 8-Bit ROM 16-Bit ROM 32-Bit ROM
GP Bus data pins Yes Yes No
SDRAM interface data pins Yes Yes Yes

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