UART Serial Ports
21-12 Élan™SC520 Microcontroller User’s Manual
21.5.7.1 Serial Port Interrupts
Each serial port supports the standard UART interrupts. These include:
■ Received data available or FIFO trigger level reached
■ Transmit Holding register empty (THRE)
■ Modem status change (including clear-to-send, data-set-ready, ring indicator, data
carrier detect)
■ Line Status register receiver interrupts (including overrun error, parity error, framing error
and break interrupt)
In 16550-compatible mode, the FIFO time-out interrupt is also enabled when the received
data available interrupt is enabled.
The UART interrupt sources and their priority are shown in Table 21-7. If two interrupt
sources are pending simultaneously, the highest priority interrupt is indicated by the ID field
of the UART x Interrupt ID (UARTxINTID) register. When the interrupt source is cleared, a
subsequent read from this port returns the next highest priority interrupt source.
Note: In 16450-compatible mode, the INT_ID2 bit always reads back 0. The INT_ID bit
field is located in the UART x Interrupt ID (UARTxINTID) register.
The UART interrupts are enabled by the Interrupt Enable register and read from the UART
x Interrupt ID (UARTxINTID) register.
21.5.7.2 DMA Interrupts
Each UART can generate an interrupt when the Transfer Count (TC) signal associated with
DMA transfers is asserted. Four enable bits and four status bits are available for these
interrupts: transmit and receive Transfer Count reached for each UART. These bits are
located in the UART x General Control (UARTxCTL) and UART x General Status
(UARTxSTA) registers.
Table 21-7 Serial Port Interrupt and Interrupt Priority
INT_ID
Bit Field Description Identification Priority
000b Modem status change Fourth (Lowest)
001b Transmit holding register empty (16540-compatible
mode)/Transmit FIFO empty (16550-compatible mode)
Third
010b Received data available (16540-compatible mode)/
Receiver FIFO trigger (16550-compatible mode)
Second
011b Receive line status First (Highest)
100b Not used —
101b Not used —
110b FIFO time-out Second
111b Not used —
To Next Page
Loading...