AMD Elan SC520 - Figure 15-4 NMI Routing

Programmable Interrupt Controller
Élan™SC520 Microcontroller User’s Manual 15-15
Figure 15-4 NMI Routing
pit_tmr0_irq
pit_tmr1_irq
pit_tmr2_irq
gp_tmr0_irq
gp_tmr1_irq
gp_tmr2_irq
uart1_irq
uart2_irq
ssi_irq
ecc_nmi
wdt_irq
rtc_irq
GPIRQ0
polarity0
GPIRQ10
polarity10
nmi_enb0
nmi_enb10
INTA
polarity11
nmi_enb11
INTD
polarity14
nmi_enb14
nmi_enb15
nmi_enb16
nmi_enb17
nmi_enb18
nmi_enb19
nmi_enb20
nmi_enb21
nmi_enb22
nmi_enb23
nmi_enb24
nmi_enb25
nmi_enb26
NMI to CPU
0
1
0
1
0
1
0
1
pci_irq
gpdma_bc_irq
nmi_enb28
nmi_enb29
nmi_trig
pci_nmi
nmi_enb27
nmi_out
nmi_enb
wpv_irq
ice_irq
nmi_enb30
nmi_enb31
ferr_irq
nmi_enb32
Notes:
The polarity control signal per external interrupt source is common to those used across the channel routers. The
gating NMI enable bits for each source are controlled via the interrupt mapping registers. The NMI conditioning logic
to implement NMI sharing is not shown in this figure