System Address Mapping
Élan™SC520 Microcontroller User’s Manual 4-11
Figure 4-3 System I/O Map
4.3.4.1 Configuration Base Address (CBAR) Register
The Configuration Base Address (CBAR) register (Port FFFCh) is a 32-bit register that is
used to relocate the integrated memory-mapped peripherals and MMCR registers, thus
allowing a more flexible system memory map. The CBAR is fixed in I/O space at FFFCh
and is “keyed” to prevent accidental programming.
The CBAR allows an alias of the memory-mapped configuration registers (MMCR) to be
aliased anywhere in the first 1 Gbyte of address space on a 4-Kbyte boundary. The MMCR
is always available in the memory space directly below the boot ROM space at FFFEF000h,
but the CBAR can be programmed to optionally allow a copy of this region anywhere in the
lower 1-Gbyte space (on a 4-Kbyte boundary).
4.3.4.2 PCI Configuration Space
PCI Local Bus Specification,
Revision 2.2, defines an indirect-mapped configuration space
that occupies only eight bytes in I/O space from 0CF8–0CFFh, and this mechanism is
supported in the ÉlanSC520 microcontroller. The PCI bus configuration scheme uses two
32-bit I/O locations:
■ PCI Configuration Address (PCICFGADR) register (Port 0CF8h) is the
address
register
where the actual address of the device’s register and the bus number is located.
■ PCI Configuration Data (PCICFGDATA) register (Port 0CFCh) is the
data
register where
the data of the specific register is written to or read from.
PC/AT Peripherals
(See Table 4-5)
The “holes” default to
external GP bus, but
can be redirected to
PCI bus. See
Section 4.3.4.4
03FFh
0000h
FFFFh
0
1 Kbyte
64 Kbytes
Default PCI Bus
Space
Can also be
retargeted to GP bus
FFFCh
CBAR
0CFFh
0CF8h
PCI Configuration
Registers
Default PCI Bus
Space
Can also be
retargeted to GP bus
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