System Initialization
Élan™SC520 Microcontroller User’s Manual 3-19
Several actions could be taken, from merely preventing the write from taking place, to killing
the offending thread, or even restarting the system. Also, the event could be recorded and/
or reported to a debugging or diagnostic interface or console port. During debugging, a
breakpoint could be set at the front of the write-protect interrupt service routine.
Assuming the system code resides in the first 768 Kbytes of SDRAM at address 0, the
value E602C000h configures a PAR register with the values shown in Table 3-12.
3.8 CONFIGURING THE INTERRUPT MAPPING
The ÉlanSC520 microcontroller has very flexible interrupt routing and control capability.
Each of the hardware interrupt sources can be mapped to any of the different interrupt
priority levels in the programmable interrupt controller (PIC).
In contrast to a basic PC, which has fixed interrupt mappings and operation, the ÉlanSC520
microcontroller has a very flexible interrupt management architecture. For full details on
this system, see Chapter 15, “Programmable Interrupt Controller”. The information in
“Interrupt Sources” on page 15-8 is of particular importance.
The following sections discuss options to be considered for the software that configures
interrupts.
3.8.1 Edge-Sensitive or Level-Triggered Interrupts
Edge- and level-triggering can be programmed for each PIC or on an interrupt-by-interrupt
basis.
For example, all of the interrupts on the Slave 2 interrupt controller could be programmed
for edge-triggered operation.
■ Setting the S2_GINT_MODE bit in the Interrupt Control (PICICR) register (MMCR offset
D00h) allows the LTIM bit in the Slave 2 PIC Initialization Control Word 1 (S2PICICW1)
register (Port 0024h) to control how interrupts are triggered for that controller.
■ If the S2_GINT_MODE bit is cleared, then the edge- or level-triggered nature is
controlled for each interrupt input to the PIC individually using the Slave 2 PIC Interrupt
Mode (SL2PICMODE) register (MMCR offset D04h).
3.8.2 Interrupt Mapping
Using the Interrupt Mapping registers, each interrupt source can be mapped to one of the
interrupt channels in the PIC block, the NMI interrupt, or can be disabled as an interrupt
input. The flexibility of the ÉlanSC520 microcontroller allows any interrupt source in the
system to trigger either a regular interrupt or an NMI.
Table 3-12 Example PAR Programming: Write-Protected Code Segments
Bit Field Value Meaning
Target Device 111b SDRAM
Attribute Field 001b Write disable, cacheable, code execution permitted
Page Size 1b 64-Kbyte granularity
Region Size Bh Specifies twelve 64-Kbyte pages for a 768-Kbyte region size
Start Address 0h Physical address 00000000h
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