Synchronous Serial Interface
Élan™SC520 Microcontroller User’s Manual 22-5
22.5.2 Configuration Information
The MSBF_ENB, CLK_INV_ENB, and PHS_INV_ENB bits in the SSI Control (SSICTL)
register (MMCR offset CD0h) define the order of the bits, the clock idle state, and the clock
edge upon which data is transmitted/received (phase).
■ The SSI should be configured to assert SSI_DO on the same clock edge that the slave
uses to transmit.
■ SSI_DI is sampled on the opposite clock edge.
22.5.2.1 Bit Order
The SSI bit order can be changed by the SSI Most Significant Bit First Mode Enable
(MSBF_ENB) bit. A byte can be transferred with the least significant bit first (LSBF) or most
significant bit first (MSBF). MSBF mode is enabled when this bit is written to a 1. This mode
is common for input and output data.
22.5.2.2 Clock Idle State
The clock idle state is controlled by the SSI Inverted Clock Mode Enable (CLK_INV_ENB)
bit. The absolute time to drive/sample is unchanged by the CLK_INV_ENB bit.
■ When the CLK_INV_ENB bit has a value of 0, SSI_CLK idles High, then pulses Low
during a transaction.
■ If the CLK_INV_ENB bit is written to a 1, the clock idle state is Low.
22.5.2.3 Clock Phase
The clock phase, relative to the serial data, is determined by the SSI Inverted Phase Mode
Enable (PHS_INV_ENB) bit.
■ In
non-inverted phase mode
, data is transmitted on odd edges of the SSI clock, and
received on even edges.Therefore, the first SSI clock edge of a transaction shifts out
the first bit on SSI_DO, if writing. SSI_DI data is latched, during a receive transaction,
on even edges of the SSI clock.
■
Inverted phase mode
requires that the SSI_DI signal be sampled on the first (odd) clock
edge(s). Consequently, the first bit is asserted on SSI_DO one-half an SSI clock cycle
before the first edge of SSI_CLK, and even edges afterwards.
22.5.3 Bus Cycles
The four possible combinations of CLK_INV_ENB and PHS_INV_ENB are shown in
Figure 22-6.
■ Microwire compatibility is configured when the PHS_INV_ENB, CLK_INV_ENB, and
MSBF_ENB bits are all set to 1.
■ The SSI is compatible with an SCP interface when the PHS_INV_ENB and
CLK_INV_ENB bits are cleared to 0, and the MSBF_ENB bit is set to 1.
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