AMD Elan SC520 - Figure 4-2 System Memory Map; Memory Space

System Address Mapping
Élan™SC520 Microcontroller User’s Manual 4-7
4.3.3 Memory Space
Memory space in the ÉlanSC520 microcontroller includes SDRAM, ROM, PCI bus, GP
bus, and the MMCR registers. A system memory map is shown in Figure 4-2.
■ The CPU has access to the entire memory space.
■ PCI bus masters and the GP bus DMA controller have access to SDRAM space only.
Characteristics of these memory spaces are defined in subsequent sections.
Figure 4-2 System Memory Map
Dedicated
PCI Bus
Space
Default is SDRAM up
to amount of SDRAM
installed. Default is PCI
from top of configured
amount of SDRAM to
256 Mbytes
0FFFFFFFh
00000000h
3FFFFFFFh
FFFFFFFFh
0
256 Mbytes
1 Gbyte
4 Gbytes
This space defaults to
SDRAM, but portions can b
e
redirected to ROM, GP bus,
or PCI bus memory via PA
R
registers; or redirected to
MMCR space, via the CBA
R
register. ROM or SDRAM
regions with noncacheable,
write-protected, and/or
execute privilege attributes
can be also be specified wit
h
the PAR registers.
Accesses from PCI bus
masters are allowed to
installed SDRAM only.
This space defaults to PCI
bus memory space, but
portions can be redirected
to ROM or GP bus via PAR
registers. Regions with
noncacheable, write-
protected, and/or execute-
protected ROM attributes
can be also be specified
with the PAR registers. Any
unused regions in this
space default to PCI.
This area is not decoded by
the ÉlanSC520
microcontroller’s host
bridge as a target.
Default PCI Bus
Space
Can also be
retargeted to
ROM or GP bus
FFFF0000h
BOOT ROM Space
Notes:
The boot ROM device
connected to BOOTCS
defaults to a 64-Kbyte
region at the top of memory.
MMCR Space
FFFEFFFFh
FFFEF000h