AMD Elan SC520 - Registers; Operation; Table 6-1 Reset Generation Registers-Memory-Mapped; Table 6-2 Reset Generation Registers-Direct-Mapped

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Reset Generation

Élan™SC520 Microcontroller User’s Manual 6-3

6.4 REGISTERS

The reset generation on the ÉlanSC520 microcontroller is controlled by the memory-

mapped registers listed in Table 6-1 and the direct-mapped registers listed in Table 6-2.

6.5 OPERATION

There are several different types of reset supported on the ÉlanSC520 microcontroller:

■ System reset

■ System reset with SDRAM retention, called

programmable reset

■ Soft CPU reset

■ GP bus reset

■ PCI reset

■ RTC reset

System reset is the primary reference reset on the ÉlanSC520 microcontroller. It is

described in “System Reset” on page 6-4.

Table 6-3 shows the ÉlanSC520 microcontroller reset sources and the functions affected.

Table 6-1 Reset Generation Registers—Memory-Mapped

MMCR

Offset

Address Function

Host Bridge Control HBCTL 60h PCI reset (RST

)

Watchdog Timer Control WDTMRCTL CB0h Watchdog timer enable, WDT reset enable,

interrupt flag, duration of the WDT time-out

interval

System Board Information SYSINFO D70h System configuration data latched on RSTLD7–

RSTLD0 pins at assertion of PWRGOOD

Reset Configuration RESCFG D72h Control bits for system reset, GP bus reset

(GPRESET), programmable SDRAM retention

reset (PRGRESET pin enable), and AMDebug

mode enable

Reset Status RESSTA D74h Reset source status: SCP reset, AMDebug hard

reset detect, AMDebug system reset, watchdog

timer time-out, CPU shutdown (soft reset),

PRGRESET pin, and PWRGOOD pin

Table 6-2 Reset Generation Registers—Direct-Mapped

SCP Data Port SCPDATA 60h System Control Processor (SCP) data write, a20

gate command emulation

SCP Command Port SCPCMD 64h SCP command write, a20 gate command

emulation, CPU reset command emulation

System Control Port A SYSCTLA 92h Soft CPU reset generation, alternate a20 control