System Address Mapping
4-20 Élan™SC520 Microcontroller User’s Manual
– All memory-mapped integrated peripherals and configuration registers for PC/AT
peripherals must be accessed as specified in the
Élan™SC520 Microcontroller
Register Set Manual
, order #22005.
– PCI configuration registers should be accessed as 32 bits unless otherwise specified
in the
Élan™SC520 Microcontroller Register Set Manual
, order #22005.
4.4 INITIALIZATION
The ÉlanSC520 microcontroller’s address decoding is cleared to the default state by a
system reset.
■ The BOOTCS decoding is enabled for the 64-Kbyte region from FFFF0000–FFFFFFFFh
■ SDRAM address space is disabled.
■ All PAR registers are disabled and cleared to zeros, which means there are no external
GP bus address spaces enabled. Note that I/O holes below 1 Kbyte will be directed to
the external GP bus. However, no chip selects are enabled, and positive decodes would
be required.
■ Integrated PC/AT peripheral I/O space is enabled as defined in Table 4-5 on page 4-13.
■ The Configuration Base Address (CBAR) register is addressed in I/O space at FFFCh.
Memory-mapped configuration register space is enabled at FFFEF000–FFFEFFFFh
(below CPU boot space address).
■ The PCI bus is disabled, and the configuration registers are defaulted to the values
specified in
PCI Local Bus Specification,
Revision 2.2. PCI configuration space is
enabled in I/O space at ports 0CF8h and 0CFCh (PCICFGADR and PCICFGDATA).
See “Programmable Address Region (PAR) Registers” on page 4-5 for information on
configuring these registers. See “Configuration Information” on page 4-14 for additional
detail on configuring the various address spaces included on the ÉlanSC520
microcontroller.
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