System Address Mapping
Élan™SC520 Microcontroller User’s Manual 4-19
potential problem is modifying a PAR register to redirect normal SDRAM region
accesses to the PCI bus, while a PCI bus master has already been granted the PCI
bus. In this case, when the CPU completes the write to the PAR register, the posted
PCI bus master access is forwarded to the SDRAM controller because the bus was
already granted to the PCI bus master. This problem can be alleviated by disabling
PCI bus master access to SDRAM (the default mode after reset) via the System Arbiter
Master Enable (SYSARBMENB) register (MMCR offset 72h), and performing a read
from an external PCI agent to flush the ÉlanSC520 microcontroller’s target FIFOs,
before writing to configuration registers that affect address decoding.
– The CPU cache should always be flushed after the cacheability attribute is changed
from cacheable to noncacheable for any memory region (by programming the PAR
register), or when the cache write policy is changed from write-back to write-through.
■ Programming the PAR register maximum region size and a page size of 64 Kbytes allows
a space up to 128 Mbytes to be defined; however, the GP bus/ROM address pins support
a maximum of 64 Mbytes per chip select. If a 128-Mbyte space is programmed for a GP
bus or ROM chip select, the upper 64 Mbytes will be aliased with the lower 64-Mbyte
region.
■ When programming PAR registers for GP bus I/O space, it is best to configure the space
on doubleword boundaries. Note that when specifying unaligned byte regions for I/O
access, the software that accesses the regions must directly address the correct byte
or bytes. For example, if a PAR is programmed with an I/O region, and the start address
is xxx1h (i.e., byte 1), when the CPU performs a word or doubleword access starting at
xxx0h (i.e., byte 0), the entire doubleword access is redirected to the PCI bus (byte 1
will not be accessed on the GP bus as programmed). In this case the byte requested
must
be directly accessed by the CPU at I/O address xxx1h.
■ A write-protection violation occurs when the CPU, any PCI bus master, or the GP-DMA
controller attempts to write to any memory region that has been marked as write-
protected by a PAR register attribute. When this occurs, the cycle is always forwarded
to SDRAM as a write cycle with the SDQM signals inactive, and the original data is
discarded. Any data that was written to the write buffer prior to enabling write-protection
is successfully written to SDRAM.
■ Software must include proper interrupt service routines and exception handlers when
enabling write-protection violation interrupts and nonexecutable region attributes in the
Address Decode Control (ADDDECCTL) register (MMCR offset 80h). Note that in the
case of the write protection violation, the PAR register number that contains the address
region of the violation is latched in the WPV_WINDOW bit field in the Write-Protect
Violation Status (WPVSTA) register (MMCR offset 82h) and retained until it is cleared
by software.
The PARx window number is latched when a write-protect violation occurs.
Subsequent write-protect violations are not captured until software clears the interrupt
by writing a 1 to the WPV_STAT bit in the same register.
■ If two or more PAR registers are overlapping (programmed to have some address range
in common), the write-protection exception is generated only if the higher priority PAR
has the attribute enabled. If the lower priority PAR has the write-protect attribute enabled
but the higher priority PAR has it disabled, then writes into the common address range
shared by the two PAR registers will
not
generate an exception. This discussion applies
to the cacheability control and code execution attributes, as well.
■ Access of ÉlanSC520 microcontroller internal configuration registers:
– All integrated PC/AT peripherals mapped to I/O space must be accessed only as 8
bits unless otherwise specified.
To Next Page
Loading...