System Address Mapping
4-18 Élan™SC520 Microcontroller User’s Manual
■ PAR registers should not be programmed to conflict with any of the fixed I/O regions,
such as the Configuration Base Address (CBAR) register or the PCI bus configuration
space.The ÉlanSC520 microcontroller’s address decoding does not permit PAR
registers to overlay the integrated PC/AT peripherals.
■ In general, the PAR register start address and region size should not be programmed
to conflict with each other. It is possible to program the PAR registers such that the region
size is greater than the start address allows. For example, if the region size is defined
as 64 Kbytes, but the start address is programmed to be the top of the 1-Gbyte region
(maximum address allowed by PAR registers) minus 4 Kbytes, then the address space
available will be the 4-Kbyte region starting at the start address.
– Subsequent access past the 1-Gbyte boundary will still be to the PCI bus
– The remaining 60-Kbyte region will
not
qualify as a PAR hit.
■ When programming the PAR registers for an SDRAM region, the PAR register start
address and region size should not conflict with the programmed value that defines the
top of SDRAM in the system. For example, if a PAR is setup for SDRAM and the region
size is defined as 8 Kbytes, but the start address is programmed to be the top of the
SDRAM minus 4 Kbytes, then addresses above the top of SDRAM will
not
result in a
hit for this PAR.
■ If the TARGET field of any PAR register is defined as SDRAM, but no SDRAM has been
enabled via the SDRAM controller configuration registers, the memory space defaults
to the PCI bus.
■ Systems that configure another memory space resource to be overlaid on top of SDRAM
space do not have access to the SDRAM that was overlaid, since address translation
is not supported in the ÉlanSC520 microcontroller. For example, if a PCI bus video card
is used in the 000A0000–000AFFFFh region (as in typical PC/AT operation), the system
will lose the 64 Kbytes of SDRAM in that region as long as the PAR register is enabled.
■ Any region that is overlaid on default SDRAM space through a PAR register or CBAR
takes priority over the SDRAM region in the decoding block. In effect, a portion of SDRAM
becomes inaccessible when this is done. If a PCI bus master generates an address to
this overlaid address region, the cycles will be forwarded to SDRAM and will be write-
protected.
■ Code execution from memory on the GP bus or the PCI bus is discouraged (after boot
code has executed), since accesses to these spaces are not cacheable and may result
in unacceptable latencies under some conditions. Code execution is more efficient when
executing from SDRAM or from ROM devices that use BOOTCS
, ROMCS1, or
ROMCS2
, because accesses to these resources are cacheable.
■ The ÉlanSC520 microcontroller guarantees coherency with SDRAM buffers that are
shared between the CPU and other bus masters, but it may be beneficial to mark these
regions as noncacheable to avoid the overhead with cache write-backs upon every
access by the bus master. This can be accomplished by programming a PAR register
and setting the noncacheable attribute. Cache snooping will continue; however, the
performance impact is negligible, since there will be no write-back cycles.
■ Care must be taken when programming configuration registers that affect address
decoding during normal system operation when either PCI bus master or GP bus DMA
activity is occurring.
– When writing to PAR registers, verify that the ÉlanSC520 microcontroller’s PCI host
bridge target FIFOs have been flushed and disable PCI bus master access of SDRAM
to prevent unexpected forwarding of accesses from other masters. An example of a
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