Architectural Overview
Élan™SC520 Microcontroller User’s Manual 1-7
1.3.9 Integrated Peripherals
The ÉlanSC520 microcontroller is a highly integrated single-chip CPU with a complete set
of integrated peripherals that are a superset of common PC/AT peripherals, plus a set of
memory-mapped peripherals that enhance its usability in various applications.
■ A programmable interrupt controller (PIC) (see Chapter 15) that provides the capability
to prioritize 22 interrupt levels, up to 15 of these being external sources. The PIC can
be programmed to operate in PC/AT-compatible mode, but also contains extended
features, including support for more sources and flexible routing that allows any interrupt
request to be steered to any PIC input. Interrupt requests can be programmed to
generate either non-maskable interrupt (NMI) or maskable interrupt requests.
■ An integrated DMA controller (see Chapter 14) is included for transferring data between
SDRAM and GP bus peripherals. The GP-DMA controller operates in single-cycle (fly-
by) mode for more efficient transfers. The GP-DMA controller can be programmed for
PC/AT compatibility, but also contains enhanced features:
– A double buffer-chaining mode provides a more efficient software interface.
– Extended address and transfer counts
– Flexible routing of DMA channels
■ Three general-purpose 16-bit timers (see Chapter 17) that provide flexible cascading
for extension to 32-bit operation. These timers provide the ability to configure down to
the resolution of four clock periods where the clock period is the 33-MHz clock. Timer
input and output pins provide the ability to interface with off-chip hardware.
■ A standard PC/AT-compatible programmable interval timer (PIT) (see Chapter 16) that
consists of three 16-bit timers.
■ A software timer (see Chapter 18) that eases the task of keeping system time. It provides
1-µs resolution and can also be used for performance monitoring.
■ A watchdog timer (see Chapter 19) to guard against runaway software.
■ A real-time clock (RTC) with battery backup capability (see Chapter 20). The RTC also
provides 114 bytes of battery-backed RAM for storage of configuration parameters.
■ Two integrated 16550-compatible UARTs (see Chapter 21) that provide full handshaking
capability with eight pins each. Enhancements enable the UARTs to operate at baud
rates up to 1.152 Mbits/s. The UARTs can be configured to use the integrated GP bus
DMA controller to transfer data between the serial ports and SDRAM.
■ A synchronous serial interface (SSI) that is compatible with SCP, SPI, and Microwire
slave devices (see Chapter 22). The SSI interface can be configured for either full-duplex
or half-duplex operation using a 4-wire or 3-wire interface.
■ 32 programmable I/O pins are provided (see Chapter 23). These pins are multiplexed
with other peripherals and interface functions.
■ The ÉlanSC520 microcontroller also provides PC/AT-compatible functions for control of
the a20 gate and the soft CPU reset (Ports 0060h, 0064h, 0092h).
1.3.10 JTAG Boundary Scan Test Interface (Chapter 25)
The ÉlanSC520 microcontroller provides a full JTAG test port that is compliant with IEEE
Std 1149.1-1990 for use during board testing.
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