Élan™SC520 Microcontroller User’s Manual 9-1
CHAPTER
9
PCI BUS HOST BRIDGE
9.1 OVERVIEW
The ÉlanSC520 microcontroller includes an integrated PCI bus host bridge, which allows
the microcontroller to interface with any PCI bus Revision 2.2-compliant master or target
device.
The PCI host bridge includes the following features:
■ 33 MHz, 32-bit PCI bus Revision 2.2-compliant
■ Peak transfer rate of 132 Mbytes/s
■ Support for delayed transactions improves PCI bus utilization
■ Support for long bursts without disconnect when the ÉlanSC520 microcontroller is a
target (64 doublewords for both reads and writes)
■ Capable of zero wait state burst transfers as a target
■ Support for advanced PCI bus commands as a target: memory-read-line, memory-read-
multiple
■ Flexible PCI bus interrupt steering logic
■ Supports fast back-to-back transactions as a PCI bus target
According to the
PCI Local Bus Specification,
Revision 2.2, the initiator, or
master
, is the
device that initiates the PCI transfer. The slave, or
target
, is the device being addressed
by the master for the data transfer.
9.2 BLOCK DIAGRAM
The ÉlanSC520 microcontroller PCI host bridge interface is shown in Figure 9-1.
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