AMD Elan SC520 - Chapter 14 Gp Bus Dma Controller; Overview; Block Diagram

Élan™SC520 Microcontroller User’s Manual 14-1
CHAPTER
14
GP BUS DMA CONTROLLER
14.1 OVERVIEW
The ÉlanSC520 microcontroller includes an integrated GP bus DMA (GP-DMA) controller.
The GP-DMA controller is designed to transfer data between external GP bus peripherals
and SDRAM. Transfers between the internal UART serial ports and SDRAM are also
supported. Throughout this document, the term
GP-DMA refers to a DMA transaction on
the GP bus.
Features of the GP bus DMA controller include:
■ Fly-by transfers between GP bus peripherals and SDRAM
■ Support for up to seven DMA request channels (with a maximum of four external
requests)
■ Two internal UART serial ports can initiate GP-DMA transfers
■ GP-DMA controller can address all of the system SDRAM
■ In enhanced GP-DMA mode:
– Four channels are individually configurable for either 8 or 16 bits.
– Maximum transfer count is 16 Mbytes (24-bit count register).
– Channel widths default to PC/AT-compatible mode (three 16-bit, and four 8-bit).
– Buffer chaining capability
■ Variable clock modes: 4, 8, and 16 MHz
■ Transfers to and from SDRAM only. No transfers are possible to PCI, ROM, or peer GP
bus devices when using the GP-DMA controller.
Note: The GP bus DMA controller is capable of supporting most ISA DMA applications
and devices. However, not all of the legacy ISA timings are supported. See the
Élan™SC520 Microcontroller Data Sheet, order #22003, for information on the GP bus and
GP-DMA timing supported by the ÉlanSC520 microcontroller.
14.2 BLOCK DIAGRAM
The GP-DMA controller consists of two DMA cores: the slave core and the master core.
■ The slave core has four 8-bit channels by default: 0, 1, 2, and 3.
■ The master core has three 16-bit channels by default: 5, 6, and 7.
■ Channel 4 must be programmed to cascade mode and must be unmasked if any of the
8-bit channels 0–3 are to be used.
■ In enhanced GP-DMA mode, Channels 3, 5, 6, and 7 are programmable to support
either 8-bit or 16-bit mode.
Figure 14-1 shows a block diagram of the GP-DMA controller. Figure 14-2 shows how the
master and slave cores are connected.