System Arbitration
Élan™SC520 Microcontroller User’s Manual 8-17
The following sequence annotates the PCI bus concurrent mode arbitration parking cycle
shown in Figure 8-10.
■ Clock #2: Master 0 requests access to the bus.
■ Clock #3: The PCI bus arbiter samples REQ asserted and begins arbitration. Master 0
is the only master requesting the bus, so the PCI bus arbiter grants the bus to master
0 by asserting GNT
0.
■ Clock #4: Master 0 samples the bus idle and its GNT0 asserted, and begins a transaction
by asserting FRAME
. Master 0 now becomes the lowest priority master in the rotating
priority queue.
■ Clock #5: The PCI bus arbiter detects a transaction has started and begins to rearbitrate
for the next master. Because no other masters are requesting the bus, the PCI bus
arbiter keeps asserting the GNT0
for master 0. This allows master 0 to continue a
transaction even after its master latency timer has expired. If another master were
requesting the bus, the PCI bus arbiter would rearbitrate, deassert the GNT0
for master
0, and assert the GNT
for the next master to be granted the bus.
■ Clock #7: Master 0 samples the end of the transaction. The PCI bus arbiter samples
FRAME
deasserted, signaling that this is the last data phase of the transaction. Because
no other masters are requesting the bus, the PCI bus arbiter will now park the bus on
the configured master (Am5
x
86 CPU). The PCI bus arbiter deasserts GNT0 to master
0 and asserts gnt
to the Am5
x
86 CPU. Note that req is not asserted. If the PCI bus arbiter
was configured to park on the last master that acquired the bus, it would keep GNT
0
asserted and park on master 0.
■ Clock #8: The Am5
x
86 CPU samples the bus idle and its gnt asserted. Note the Am5
x
86
CPU does not have to start a transaction, but it does need to drive the shared PCI bus
signals to stable values. If the Am5
x
86 CPU wants to start a transaction, it does not have
to assert req
and wait for gnt. It can assert FRAME and begin a transaction on any clock
it samples gnt
asserted. The master on which the PCI bus is parked has no arbitration
latency.
■ Clock #10: Master 0 requests the bus by asserting REQ0.
■ Clock #11: The PCI bus arbiter samples REQ asserted and begins arbitration. Master
0 is the only master requesting the bus, so the PCI bus arbiter determines that master
0 will be the next master to be granted the bus. The PCI bus arbiter then deasserts gnt
to the Am5
x
86 CPU.
■ Clock #12: The PCI bus arbiter asserts GNT0. Note the PCI bus arbiter cannot
simultaneously deassert one master’s GNT
and assert another master’s GNT when the
bus is idle. Doing so could cause contention on the shared PCI bus signals.
■ Clock #13: Master 0 samples the bus idle and its GNT0 signal asserted and begins a
transaction by asserting FRAME
. Master 0 now becomes the lowest priority master in
the rotating priority queue. Note that there is a two-clock arbitration latency for masters
that are not parked on the bus when the bus is idle. This is because, when the bus is
idle, one GNT
cannot be asserted on the same clock when another GNT is deasserted.
Therefore, GNT
to the master the bus is parked on will be deasserted in one clock, and
the GNT
to the next master granted the bus will be asserted one clock later, resulting in
a two-clock arbitration latency.
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