PCI Bus Host Bridge
9-30 Élan™SC520 Microcontroller User’s Manual
c. Program the ÉlanSC520 microcontroller-specific PCI host bridge configuration (write
posting, retry time-out counter, interrupts, etc.). Note that write-posting must be
disabled while operating in nonconcurrent arbitration mode. See Chapter 8, “System
Arbitration”, for further details on nonconcurrent mode arbitration.
d. Program the standard PCI bus configuration registers. See “Configuration Information”
on page 9-9 for more information.
2. Configure the external PCI bus devices.
In general, PCI host bridge configuration bits should not be changed except during a PCI
bus initialization after a system or programmable reset.
A PCI bus 2.2-compliant target is not required to meet the normal initial latency time limit
if it is accessed during the 2
25
clock periods (about one second) following RST signal
deassertion. During this time, an addressed target is permitted to do any of the following:
■ Initiate a retry.
■ Claim the access and hold in wait states until ready to respond.
■ Ignore the access.
A device that ignores the access is essentially not recognized if the initialization software
tries to configure it too soon after RST
is deasserted, resulting in an incomplete system
configuration. To support such devices, the initialization software might need to include a
delay to ensure that 2
25
clock periods pass before PCI devices are configured.
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