PCI Bus Host Bridge
Élan™SC520 Microcontroller User’s Manual 9-25
■ Clock #12: The external PCI bus master retries the delayed transaction. While a delayed
transaction is pending, all other read transactions are retried by the host bridge (these
are not latched as delayed transactions). Write transactions, however, are allowed to
complete and are put into the write FIFO. If the external PCI master retries the delayed
transaction before the host bridge has read the first doubleword of data into the target
read FIFO, the host bridge issues another retry to the external PCI bus master (and
keeps issuing retries until the first doubleword of data has been read into the target read
FIFO).
■ Clock #14: By now, the PCI host bridge has read in the first doubleword of data into the
target read FIFO and recognizes this transaction as the pending delayed transaction.
The host bridge asserts DEVSEL
to claim the transaction.
■ Clock #16: The PCI host bridge asserts TRDY for the first data phase of the transaction.
After the first data phase, the host bridge can burst up to the next cache-line boundary
without adding anymore wait states. After each cache line, the PCI host bridge may
insert wait states if the target read FIFO becomes empty.
■ Clocks #17–#19: The external PCI master reads the data from the PCI host bridge.
(Although the figure shows it this way, note that SDRAM having the data by Clock #17
is quite optimistic.) The external PCI bus master can insert wait states into the transaction
by deasserting IRDY
. Clock #19 is the last data requested by the external PCI bus master
(FRAME
deasserted, IRDY asserted).
9.5.4.9.3 PCI Host Bridge Target Disconnect
Figure 9-16 shows the PCI host bridge target controller issuing a disconnect to an external
PCI bus master. This example shows a disconnect during an external PCI bus master write
cycle, but the mechanism is the same for external PCI bus master read cycles. The only
difference is that Clock #2 is a turnaround cycle on AD31–AD0 bus. The PCI host bridge
issues a disconnect if:
■ During an external PCI bus master write cycle, the write FIFO becomes full or 64
consecutive doublewords have been written by the bus master.
■ During an external PCI bus master read cycle, the target read FIFO becomes empty—
Note that for memory-read and memory-read-line commands, the PCI host bridge can
burst up to the next cache-line boundary without disconnecting; for memory-read-
multiple commands, the PCI host bridge can burst 64 doublewords without
disconnecting. If the external PCI bus master wishes to burst beyond these limits, then
the PCI host bridge may issue a disconnect.
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