SDRAM Controller
Élan™SC520 Microcontroller User’s Manual 10-19
For example, if an SDRAM device is organized as 2M x 8 x 4 banks (8Mb x 8) with 4096
rows and 512 columns and requires a 64-ms refresh interval, by using Table 10-11, the
refresh rate is 15.6 µs.
During an SDRAM refresh period, all enabled banks are issued an Auto Refresh command.
However, during a refresh cycle, SDRAM devices require a somewhat large amount of
current, which could become quite large when considering a simultaneous refresh of
multiple banks within the same clock period. To prevent this, the SDRAM controller staggers
the bank refresh by selecting one bank at a time. This results in only one bank being issued
an Auto Refresh command during any given clock, rather than all banks within the same
clock. This method results in a slightly larger amount of overhead associated with refresh
cycles, but prevents large current surges to the SDRAM banks on the system circuit board.
Figure 10-12 on page 10-27 shows an SDRAM staggered refresh cycle.
SDRAM refresh cycles must be enabled only when the SDRAM Operation Mode Select
specifier is in normal SDRAM mode. The Refresh Enable (RFSH_ENB) bit is located in the
SDRAM Control (DRCCTL) register (MMCR offset 10h).
10.5.5.2 Drive-Strength Selection
The ÉlanSC520 microcontroller provides selectable drive strength options on all address,
data and control signals to provide support for different SDRAM device loads presented by
different system designs.
Pins with selectable drive strength options include:
■ MA12–MA0 (memory address)
■ BA1–BA0 (bank address)
■ MD31–MD0 (memory data)
■ MECC6–MECC0 (ECC data)
■ SCS3–SCS0
■ SDQM3–SDQM0
■ SCASA–SCASB
■ SRASA–SRASB
■ SWEA–SWEB
With the exception of SCS3
–SCS0, these pins are equipped to drive 12 mA, 18 mA or 24
mA of current. SCS3
–SCS0 drive either 18 mA or 12 mA.
The SDRAM interface drive strength can be changed in the Drive Strength Control (DSCTL)
register (MMCR offset C28h), which is described in the Programmable I/O section of the
Élan™SC520 Microcontroller Register Set Manual
, order #22005.
10.5.5.3 Write Buffer Test Mode
The ÉlanSC520 microcontroller supports a write buffer test mode, using the alternate
function of the CF_ROM_GPCS
, DATASTRB, and CF_DRAM pins that provide master
contribution information. As WBMSTR2–WBMSTR0, these three pins indicate whether the
Am5
x
86 CPU, PCI bus master, GP-DMA, or a combination of these (because the write
buffer may collapse or merge write data) has contributed into the rank of the write buffer
currently in the process of being written to SDRAM. This option is specified with the
WB_TST_ENB bit in the SDRAM Control (DRCCTL) register (MMCR offset 10h). See
Chapter 24, “System Test and Debugging”, for more information on the uses of these pins.
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