Table of Contents
xxii Élan™SC520 Microcontroller User’s Manual
Table 13-1 GP Bus Signals Shared with Other Interfaces. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-3
Table 13-2 GP Bus Registers—Memory-Mapped . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-5
Table 13-3 GP Bus Echo Mode Minimum Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-9
Table 13-4 Cross-Reference Table of ISA Signals and GP Bus Signals. . . . . . . . . . . . . . . . . . 13-12
Table 13-5 Example Super I/O Controller Interface Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-13
Table 13-6 Example AMD Enhanced Serial Communications Controller Interface Timing . . . . 13-15
Table 13-7 Differentiating Upper/Lower Byte Access of 16-Bit Devices . . . . . . . . . . . . . . . . . . 13-19
Table 13-8 Dynamic Bus Sizing Override of Programmed Data Width . . . . . . . . . . . . . . . . . . . 13-20
Table 14-1 GP-DMA Signals Shared with Other Interfaces. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-4
Table 14-2 GP-DMA Controller Registers—Memory-Mapped. . . . . . . . . . . . . . . . . . . . . . . . . . . 14-4
Table 14-3 GP-DMA Controller Registers—Direct-Mapped . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-7
Table 14-4 Supported GP-DMA Initiator/Target Combinations . . . . . . . . . . . . . . . . . . . . . . . . . . 14-9
Table 14-5 GP-DMA Channel Mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-10
Table 14-6 8-Bit GP-DMA Channel Address Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-12
Table 14-7 16-Bit GP-DMA Channel Address Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-12
Table 14-8 GP-DMA Cycle Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-16
Table 15-1 Programmable Interrupt Controller Signals Shared with Other Interfaces . . . . . . . . 15-2
Table 15-2 Programmable Interrupt Controller Registers—Memory-Mapped. . . . . . . . . . . . . . . 15-4
Table 15-3 Programmable Interrupt Controller Registers—Direct-Mapped. . . . . . . . . . . . . . . . . 15-6
Table 15-4 PC/AT Interrupt Channel Mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-12
Table 16-1 Programmable Interval Timer Signals Shared with Other Interfaces. . . . . . . . . . . . . 16-1
Table 16-2 Programmable Interval Timer Configuration Registers—Memory-Mapped. . . . . . . . 16-2
Table 16-3 Programmable Interval Timer Configuration Registers—Direct-Mapped . . . . . . . . . 16-3
Table 16-4 PIT Internal Clock Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-6
Table 16-5 PIT External Clock Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-6
Table 17-1 General-Purpose Timer Signals Shared with Other Interfaces . . . . . . . . . . . . . . . . . 17-1
Table 17-2 General-Purpose Timer Registers—Memory-Mapped . . . . . . . . . . . . . . . . . . . . . . . 17-2
Table 17-3 GP Timers Internal Clock Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-5
Table 17-4 GP Timers External Clock Sources (Using a 33.333 MHz Crystal). . . . . . . . . . . . . . 17-6
Table 18-1 Software Timer Configuration Registers—Memory-Mapped. . . . . . . . . . . . . . . . . . . 18-2
Table 19-1 Watchdog Timer Registers—Memory-Mapped . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-2
Table 19-2 Watchdog Timer Time-Out Duration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-4
Table 20-1 Real-Time Clock Registers—Memory-Mapped . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-6
Table 20-2 Real-Time Clock Registers—Direct-Mapped. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-6
Table 20-3 Real-Time Clock Registers—RTC Indexed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-6
Table 20-4 Using RATE_SEL to Specify a Periodic Interrupt Rate . . . . . . . . . . . . . . . . . . . . . . . 20-8
Table 21-1 UART Signals Shared with Other Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-2
Table 21-2 Connection of DTE to DTE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-3
Table 21-3 UART Registers—Memory-Mapped . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-3
Table 21-4 UART Registers—Direct-Mapped . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-4
Table 21-5 Baud Rates, Divisors, and Clock Source. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-9
Table 21-6 UART Interrupt Programming Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-11
Table 21-7 Serial Port Interrupt and Interrupt Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-12
Table 22-1 Synchronous Serial Interface Registers—Memory-Mapped . . . . . . . . . . . . . . . . . . . 22-2
Table 23-1 PIO Signals Shared with Other Interfaces. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-3
Table 23-2 PIO Registers—Memory-Mapped . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-4
Table 23-3 PIO Configuration Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-5
Table 24-1 System Test and Debugging Signals Shared with Other Interfaces . . . . . . . . . . . . . 24-2
Table 24-2 System Test and Debugging Registers—Memory-Mapped. . . . . . . . . . . . . . . . . . . . 24-2
Table 24-3 WBMSTR2–WBMSTR0 Pin Definition During Write Buffer Write Cycles . . . . . . . . . 24-8
Table 24-4 WBMSTR2–WBMSTR0 Pin Definition During SDRAM Read Cycles . . . . . . . . . . . . 24-9
Table 25-1 Chip Test and Debugging Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-2
Table 25-2 Test Access Port Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-3
Table 25-3 Main Data Scan Path. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-5
Table 26-1 AMDebug Technology Connector Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-3
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