Broadcom NetXtreme/NetLink BCM5718 Series - Page 38

List of FiguresBCM5718 Programmer’s Guide
Broadcom®
January 29, 2016 • 5718-PG108-R Page 38
Figure 36: Low-Priority Mailbox Access for Indirect Mode............................................................................. 178
Figure 37: Standard Memory Mapped I/O Mode ........................................................................................... 179
Figure 38: Memory Window Base Address Register ..................................................................................... 180
Figure 39: Standard Mode Memory Window ................................................................................................. 181
Figure 40: Techniques for Accessing Ethernet Controller Local Memory ...................................................... 182
Figure 41: PCI Command Register................................................................................................................ 184
Figure 42: PCI Base Address Register .......................................................................................................... 185
Figure 43: PCI Base Address Register Bits Read in Standard Mode ............................................................ 185
Figure 44: Read and Write Channels of DMA Engine ................................................................................... 186
Figure 45: Power State Transition Diagram................................................................................................... 189
Figure 46: WOL Functional Block Diagram.................................................................................................... 213
Figure 47: Comparing Ethernet Frames Against Available Patterns (10/100 Ethernet WOL) ....................... 216
Figure 48: Unused Rows and Rules Must Be Initialized with Zeros .............................................................. 217
Figure 49: Basic Driver Interrupt Service Routine Flow ................................................................................. 232
Figure 50: Traditional Interrupt Scheme ........................................................................................................ 236
Figure 51: Message-Signaled Interrupt Scheme ........................................................................................... 237
Figure 52: MSI Data FIeld.............................................................................................................................. 238
Figure 53: IOV Receive Flow ......................................................................................................................... 267
Figure 54: Copper PHY Register Mapping Table .......................................................................................... 499
Figure 55: SerDes PHY Register Map ........................................................................................................... 549
Figure 56: File Transfer Scenario: FTP Session Begins ................................................................................ 575
Figure 57: File Transfer Scenario: Speed Mismatch...................................................................................... 575
Figure 58: File Transfer Scenario: Speed Buffers Run Low .......................................................................... 576
Figure 59: File Transfer Scenario: Switch Backpressure............................................................................... 577
Figure 60: File Transfer Scenario: Switch Flow Control................................................................................. 577
Figure 61: File Transfer Scenario: File Transfer Complete............................................................................ 578
Figure 62: Pause Control Frame.................................................................................................................... 578