List of TablesBCM5718 Programmer’s Guide
Broadcom®
January 29, 2016 • 5718-PG108-R Page 39
List of Tables
Table 1: Register Access Methods .................................................................................................................. 44
Table 2: BCM5718 Family Product Features ................................................................................................... 47
Table 3: Family Revision Levels ...................................................................................................................... 49
Table 4: Ring Control Block Format................................................................................................................. 71
Table 5: Flag Fields for a Ring ......................................................................................................................... 71
Table 6: Send RCBs for Multiple Rings ........................................................................................................... 72
Table 7: High Priority Mail Box Registers for VRQ Rings ................................................................................ 72
Table 8: Send Buffer Descriptors Format ........................................................................................................ 75
Table 9: Defined Flags for Send Buffer Descriptors ........................................................................................ 75
Table 10: Receive Return Rings ...................................................................................................................... 78
Table 11: Receive Descriptors Format ............................................................................................................ 78
Table 12: Defined Flags for Receive Buffers ................................................................................................... 79
Table 13: Defined Error Flags for Receive Buffers .......................................................................................... 80
Table 14: Status Block Format (MSI-X Single-Vector or INTx — RSS Mode).................................................. 83
Table 15: Status Block Format (MSI-X Single-Vector or INTx — RSS Mode).................................................. 84
Table 16: Status Block [0] Format (MSI-X Multivector RSS Mode) ................................................................. 85
Table 17: Status Blocks [1 thru 4] Formats (MSI-X Multivector RSS Mode).................................................... 85
Table 18: Status Block Host Addresses and INT MailBox Addresses ............................................................. 86
Table 19: Status Word Flags ........................................................................................................................... 86
Table 20: Mailbox Registers ............................................................................................................................ 92
Table 21: Receive Rules Configuration Register ............................................................................................. 95
Table 22: Receive BD Rules Control Register ................................................................................................. 96
Table 23: Receive List Placement Rules Array (memory offset 0x480–0x4ff)................................................. 96
Table 24: Receive BD Rules Value/Mask Register.......................................................................................... 97
Table 25: Frame Format with 802.1Q VLAN Tag Inserted .............................................................................. 99
Table 26: Send Data Initiator Mode Register (Offset: 0xC00) ....................................................................... 111
Table 27: ISO Send Data Initiator Mode Register (Offset: 0xD00) ................................................................ 111
Table 28: Read DMA Mode Register (offset: 0x4800) ................................................................................... 111
Table 29: ISO Read DMA Mode Register (Offset: 0x4A00)........................................................................... 111
Table 30: Flag Field Description .................................................................................................................... 113
Table 31: Receive BD Error Flags ................................................................................................................. 119
Table 32: Receive BD Flags .......................................................................................................................... 120
Table 33: Receive BD Flags .......................................................................................................................... 122
Table 34: Send Buffer Descriptor Flags ......................................................................................................... 123
Table 35: Status Block ................................................................................................................................... 124