Revision HistoryBCM5718 Programmer’s Guide
Broadcom®
January 29, 2016 • 5718-PG108-R Page 4
5718-PG-105-R 02/24/12 Updated:
• Table 3: “Family Revision Levels,” on page 48
• Table 5: “Flag Fields for a Ring,” on page 70
• Figure 24: “Ring Control Block,” on page 118
• “Summary of Register Settings to Support Jumbo Frames” on page 126
• “Initialization Procedure” on page 136
• “Reading a PHY Register” on page 186
• “Writing a PHY Register” on page 187
• “Subsystem ID/Vendor ID Register (offset: 0x2C)” on page 251
• “DMA Read/Write Control Register (Offset: 0x6c)” on page 258
• “PCI State Register (offset: 0x70)” on page 259
• “Receive BD Standard Producer Ring Index Register (offset: 0x268-
0x26f)” on page 281
• “Transmit MAC Status Register (offset: 0x460)” on page 296
• “Receive MAC Mode Register (offset: 0x468)” on page 297
• “Statistics Registers” on page 319
• “H2B Statistics Registers” on page 320
• “Receive Data and Receive BD Initiator Mode Register (offset: 0x2400)”
on page 341
• “Link Speed 10 MB/No Link Power Mode Clock Policy Register (offset:
0x3604)” on page 356
• “Link Speed 100 MB Power Mode Clock Policy Register (offset: 0x3608)”
on page 357
• “Link Aware Power Mode Clock Policy Register (offset: 0x3610)” on
page 359
• “D0u Clock Policy Register (offset: 0x3614)” on page 360
• “Link Idle Power Mode Clock Policy Register (offset: 0x3618)” on
page 360
• “APE CLK Policy Register (offset: 0x361C)” on page 361
• “APE Sleep State Clock Policy Register (offset: 0x3620)” on page 363
• “Clock Speed Override Policy Register (offset: 0x3624)” on page 364
• “Clock Status Register (offset: 0x3630)” on page 367
• “Padring Control Register (offset: 0x3668)” on page 376
• “Receive Coalescing Ticks Register (offset: 0x3C08)” on page 393
• “Send Coalescing Ticks Register (offset: 0x3C0C)” on page 394
• “Receive Max Coalesced BD Count Register (offset: 0x3C10)” on
page 395
• “Send Max Coalesced BD Count Register (offset: 0x3C14)” on page 397
• “Status Block Host Address Register (offset: 0x3C38)” on page 400
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