Broadcom NetXtreme/NetLink BCM5718 Series - Page 41

List of TablesBCM5718 Programmer’s Guide
Broadcom®
January 29, 2016 • 5718-PG108-R Page 41
Table 71: Send Buffer Descriptor (Little-Endian 32-Bit format) with Word Swapping .................................... 201
Table 72: Send Buffer Descriptor (Big-Endian 32-bit format) with Byte Swapping ........................................ 201
Table 73: Send Buffer Descriptor (Big-Endian 32-bit format) with Word and Byte Swapping ....................... 202
Table 74: Required Memory Regions for WOL Pattern ................................................................................. 214
Table 75: 10/100 Mbps Mode Frame Patterns Memory ................................................................................ 217
Table 76: Frame Control Field for 10/100 Mbps Mode .................................................................................. 217
Table 77: Example of Splitting 10/100 Mbps Frame Data in Pattern Data Structure ..................................... 218
Table 78: Firmware Mailbox Initialization ....................................................................................................... 219
Table 79: Recommended Settings for PHY Auto-Negotiation ....................................................................... 219
Table 80: WOL Mode Clock Inputs ................................................................................................................ 219
Table 81: Magic Packet Detection Logic Enable ........................................................................................... 220
Table 82: Integrated MAC WOL Mode Control Registers ..............................................................................220
Table 83: Transmit MAC Watermark Recommendation ................................................................................ 224
Table 84: Pause Quanta ................................................................................................................................ 224
Table 85: Keep_Pause Recommended Value ............................................................................................... 224
Table 86: Statistic Block................................................................................................................................. 225
Table 87: Integrated MAC Flow Control Registers ........................................................................................ 226
Table 88: NetXtreme Legacy Status Block Format ........................................................................................ 229
Table 89: Interrupt-Related Registers............................................................................................................ 235
Table 90: MSI-X Vector Mode Selection........................................................................................................ 241
Table 91: MIS-X Status-Block and Mail Box Addresses ................................................................................ 244
Table 92: Status Block Format (MSI-X Single-Vector RSS Mode) ................................................................ 247
Table 93: Status Block format (MSI-X Single-Vector IOV Mode)................................................................... 247
Table 94: Status Block [0] Format (MSI-X Multivector RSS Mode]................................................................ 248
Table 95: Status Block [1  N  4] Formats (MSI-X Multivector RSS Mode)................................................. 249
Table 96: Status Block [0] Format (MSI-X Multivector IOV Mode)................................................................. 249
Table 97: Status Block [1  N  16] Format (MSI-X Multivector IOV Mode) ................................................. 250
Table 98: MSI-X Capability Structure............................................................................................................. 250
Table 99: MSI-X Table and PBA Structures in BCM5718 Family .................................................................. 252
Table 100: MSI-X Host Coalescing Parameters ............................................................................................ 256
Table 101: BCM5718 Family Register Map ................................................................................................... 269
Table 102: Receive BD Jumbo Producer Ring Index Register (offset: 0x270) .............................................. 307
Table 103: High Priority Mail Box Registers for VRQ Rings .......................................................................... 308
Table 104: Send BD Diagnostic Initiator ........................................................................................................ 354
Table 105: Multiple Send Ring Mail Boxes .................................................................................................... 355
Table 106: BD Fetch Limit Register (Offset 0x2D08)..................................................................................... 375
Table 107: HC Parameter Set Reset Register (Offset: 0x3C28) ................................................................... 421