Freescale Semiconductor PowerPC e500 Core

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Execution Timing

PowerPC e500 Core Family Reference Manual, Rev. 1

Freescale Semiconductor 4-37

lbz 3:1 —

lbzu 3:1

—

lbzux 3:1

—

lbzx 3:1 —

lha 3:1 —

lhau 3:1

—

lhaux 3:1

—

lhax 3:1 —

lhbrx 3:1 —

lhz 3:1 —

lhzu 3:1

—

lhzux 3:1

—

lhzx 3:1 —

lmw 2 + n —

lwarx 3Presync

lwbrx 3:1 —

lwz 3:1 —

lwzu 3:1

—

lwzux 3:1

—

lwzx 3:1 —

mbar 3:1 Store serialized

msync Latency depends on bus response time. Store and postsync serialized.

stb 3:1 Store

stbu 3:1

Store

stbux 3:1

Store

stbx 3:1 Store

sth 3:1 Store

sthbrx Store

sthu 3:1

Store

sthux 3:1

Store

sthx 3:1 Store

stmw 3 + n Store

stw 3:1 Store

stwbrx 3:1 Store

Table 4-7. LSU Instruction Latencies (continued)

Mnemonic Cycles (Latency:Throughput)

Serialization

Main Page

Default Chapter5
- Table of Contents5
Paragraph Page6
Number Title Number6
Figure Page24
Number Title Number24
- Powerpc E500 Core Family Reference Manual24
Chapter 1 Core Complex Overview39
- Overview39
  - E500 Core Complex Block Diagram40
- Upward Compatibility41
- Core Complex Summary41
- E500 Processor and System Version Numbers43
- Features43
- Vector and Floating-Point Apus44
  - Four-Stage MU Pipeline, Showing Divide Bypass46
  - Three-Stage Load/Store Unit47
- E500V2 Differences49
- Instruction Set50
- Instruction Flow52
- Initial Instruction Fetch52
- Branch Detection and Prediction52
- E500 Execution Pipeline54
  - GPR Issue Queue (GIQ)55
- Programming Model56
  - E500 Core Programming Model57
- On-Chip Cache Implementation58
- Interrupts and Exception Handling58
- Exception Handling58
- Interrupt Classes59
- Interrupt Types59
- Upper Bound on Interrupt Latencies60
- Interrupt Registers60
- Memory Management62
  - MMU Structure63
- Address Translation64
- MMU Assist Registers (MAS0-MAS4 and MAS6-MAS7)65
- Process ID Registers (PID0-PID2)66
- TLB Coherency66
- Memory Coherency67
- Atomic Update Memory References67
- Memory Access Ordering67
- Cache Control Instructions67
- Programmable68
- Core Complex Bus (CCB)68
- Performance Monitoring68
- Global Control Register69
- Performance Monitor Counter Registers69
- Local Control Registers69
- Legacy Support of Powerpc Architecture70
- Instruction Set Compatibility70
- User Instruction Set70
- Supervisor Instruction Set70
- Memory Subsystem71
- Exception Handling71
- Memory Management71
- Reset72
- Little-Endian Mode72
Chapter 2 Register Model73
- Overview73
- E500 Register Model74
- E500 Register Model75
- Special-Purpose Registers (Sprs)77
- Registers for Integer Operations81
- General-Purpose Registers (Gprs)81
- Integer Exception Register (XER)81
- Registers for Branch Operations81
- Condition Register (CR)81
- Link Register (LR)82
- Count Register (CTR)82
- Processor Control Registers82
- Machine State Register (MSR)82
- Processor ID Register (PIR)84
- Processor Version Register (PVR)85
- System Version Register (SVR)85
- Timer Registers86
- Timer Control Register (TCR)87
- Timer Status Register (TSR)88
- Time Base (TBU and TBL)88
- Decrementer Register (DEC)88
- Decrementer Auto-Reload Register (DECAR)88
- Alternate Time Base Registers (ATBL and ATBU)88
- Alternate Time Base Upper (ATBU)89
- Interrupt Registers89
- Interrupt Registers Defined by Book E90
- Save/Restore Register 0/1 (SRR0 and SRR1)90
- Critical Save/Restore Register 0/1 (CSRR0 and CSRR1)90
- Data Exception Address Register (DEAR)90
- Interrupt Vector Prefix Register (IVPR)91
- Interrupt Vector Offset Registers (Ivors)91
- Exception Syndrome Register (ESR)92
- E500-Specific Interrupt Registers94
- Machine Check Save/Restore Register 0 (MCSRR0)94
- Machine Check Save/Restore Register 1 (MCSRR1)94
- Machine Check Address Register (MCAR)94
- Machine Check Syndrome Register (MCSR)95
- Software-Use Sprs (SPRG0-SPRG7 and USPRG0)96
- Branch Target Buffer (BTB) Registers96
- Branch Buffer Entry Address Register (BBEAR)97
- Branch Buffer Target Address Register (BBTAR)97
- Branch Unit Control and Status Register (BUCSR)98
- Hardware Implementation-Dependent Registers99
- Hardware Implementation-Dependent Register 0 (HID0)99
- Hardware Implementation-Dependent Register 1 (HID1)101
- L1 Cache Configuration Registers103
- L1 Cache Control and Status Register 0 (L1CSR0)103
- L1 Cache Control and Status Register 1 (L1CSR1)105
- L1 Cache Configuration Register 0 (L1CFG0)106
- L1 Cache Configuration Register 1 (L1CFG1)107
- MMU Registers107
- Process ID Registers (PID0-PID2)108
- MMU Control and Status Register 0 (MMUCSR0)108
- MMU Configuration Register (MMUCFG)109
- TLB Configuration Registers (Tlbncfg)109
- TLB0 Configuration Register (TLB0CFG)110
- TLB1 Configuration Register 1 (TLB1CFG)111
- MMU Assist Registers (MAS0-MAS4, MAS6-MAS7)111
- MAS Register 0 (MAS0)112
- MAS Register 1 (MAS1)113
- MAS Register 2 (MAS2)114
- MAS Register 3 (MAS3)115
- MAS Register 4 (MAS4)115
- MAS Register 6 (MAS6)116
- MAS Register 7 (MAS7)-E500V2 Only117
- Debug Registers117
- Debug Control Registers (DBCR0-DBCR2)118
- Debug Control Register 0 (DBCR0)118
- Debug Control Register 1 (DBCR1)118
- Debug Control Register 2 (DBCR2)119
- Debug Status Register (DBSR)119
- Instruction Address Compare Registers (IAC1-IAC4)120
- Data Address Compare Registers (DAC1-DAC2)120
- SPE and SPFP APU Registers121
- Signal Processing and Embedded Floating-Point Status and Control Register (SPEFSCR)121
- Accumulator (ACC)124
- Performance Monitor Registers (Pmrs)124
- Global Control Register 0 (PMGC0)125
  - User Performance Monitor Global Control Register 0 (UPMGC0)125
- User Global Control Register 0 (UPMGC0)126
- Local Control a Registers (Pmlca0-Pmlca3)127
- User Local Control a Registers (Upmlca0-Upmlca3)128
- Local Control B Registers (Pmlcb0-Pmlcb3)128
- User Local Control B Registers (Upmlcb0-Upmlcb3)129
- Performance Monitor Counter Registers (PMC0-PMC3)129
- User Performance Monitor Counter Registers (UPMC0-UPMC3)130
- Synchronization Requirements for Sprs130
- Instruction Model131
- Operand Conventions131
- Data Organization in Memory and Data Transfers131
- Alignment and Misaligned Accesses132
- Unsupported Book E Instructions133
- Instruction Set Summary135
- Classes of Instructions136
  - Synchronization Requirements for E500-Specific Sprs138
Synchronization with Tlbwe and Tlbivax Instructions140
- Context Synchronization141
- Instruction-Related Interrupts142
- Load and Store Instructions147
  - Integer Load and Store Address Generation148
- Register Indirect with Index Addressing for Integer Loads/Stores149
- Branch and Flow Control Instructions153
Number159
- Performance Monitor159
- Memory Control Instructions167
- User-Level Cache Instructions167
- Supervisor-Level Instructions169
- System Linkage Instructions169
- Supervisor-Level Cache Instruction170
- Supervisor-Level Memory Control Instructions170
- Supervisor-Level TLB Management Instructions171
- Recommended Simplified Mnemonics172
- Book E Instructions with Implementation-Specific Features173
- E500 Instructions173
- Context Synchronization174
- Memory Access Alignment Support174
- Acquire Lock and Import Shared Memory175
- Lock Acquisition and Import Barriers175
- Obtain Pointer and Import Shared Memory175
Using Msync and Mbar to Order Memory Accesses175
- Export Shared Memory and Release Lock176
- Lock Release and Export Barriers176
Export Shared Memory and Release Lock Using Mbar (MO = 0)177
- Safe Fetch177
- Update Instructions177
- EIS-Defined Instructions and Apus Implemented on the E500178
- Memory Synchronization178
- SPE and Embedded Floating-Point Apus179
- SPE and Floating-Point APU GPR Usage180
- SPE Operands: Signed Fractions181
- Integer and Fractional Operations182
- SPE APU Instructions182
- SPE Integer and Fractional Operations182
- Embedded Floating-Point APU Instructions188
Integer Select (Isel) APU190
- Performance Monitor APU190
- Cache Locking APU191
- Branch Target Buffer (BTB) Locking Instructions193
- E500-Specific Instructions193
- Machine Check APU193
- Instruction Listing196
- Execution Timing203
- Terminology and Conventions203
- Instruction Timing Overview206
- E500 Instruction Flow Diagram-Details207
- GPR Issue Queue (GIQ)209
- Execution Pipeline Stages and Events211
- General Timing Considerations212
- General Instruction Flow213
- Instruction Fetch Timing Considerations214
- Interrupts Associated with Instruction Fetching214
- L1 and L2 TLB Access Times214
- Cache-Related Latency215
- Dispatch, Issue, and Completion Considerations216
- GPR and CR Rename Register Operation217
- Instruction Serialization217
- LR and CTR Shadow (Speculative) Registers217
- Interrupt Latency218
Msync Instruction Timing Considerations219
- Branch Instructions and Completion220
- Branch Unit Execution220
- Execution220
- Branch Completion (LR/CTR Write-Back)221
- BTB Branch Prediction and Resolution222
- BTB Operations223
- Fetch Group Addresses224
- BTB Locking225
- BTB Locking APU Programming Model226
- BTB Operations Controlled by BUCSR226
- BTB Special Cases-Phantom Branches and Multiple Matches227
- Load/Store Unit Execution227
- Load/Store Unit Queueing Structures227
- Cache/Core Interface Unit Integration228
- Simple and Multiple Unit Execution229
- MU Divide Execution230
- Load/Store Execution231
- MU Floating-Point Execution231
- Effect of Operand Placement on Performance232
- Memory Performance Considerations232
- Instruction Latency Summary233
- Instruction Scheduling Guidelines246
- Dispatch Unit Resource Requirements247
- Dynamic Prediction Versus no Branch Prediction247
- Fetch/Branch Considerations247
- Position-Independent Code247
- Branch Issue Queue (BIQ)248
- Completion Unit Resource Requirements248
- Dispatch Groupings248
- General Issue Queue (GIQ)248
- Issue Queue Resource Requirements248
- Completion Groupings249
- Execution Unit Considerations249
- Serialization Effects249
- SU Considerations249
- Load/Store Interaction250
- LSU Considerations250
- MU Considerations250
- Misalignment Effects251
- Load Miss Pipeline252
- Interrupts and Exceptions253
- Overview253
- E500 Interrupt Definitions254
- Recoverability from Interrupts256
- Interrupt Registers257
- Exceptions260
- Interrupt Classes261
- Interrupt Processing262
- Requirements for System Reset Generation262
- Interrupt Definitions264
- Critical Input Interrupt265
- Machine Check Interrupt266
- Core Complex Bus (CCB) and L1 Cache Machine Check Errors268
- Cache Parity Error Injection270
- Data Storage Interrupt271
- Instruction Storage Interrupt272
- External Input Interrupt273
- Alignment Interrupt274
- Program Interrupt276
- Decrementer Interrupt277
- System Call Interrupt277
- Fixed-Interval Timer Interrupt278
- Data TLB Error Interrupt279
- Watchdog Timer Interrupt279
- Instruction TLB Error Interrupt281
- Debug Interrupt282
- EIS-Defined Interrupts283
- Spe/Embedded Floating-Point APU Unavailable Interrupt283
- Embedded Floating-Point Data Interrupt284
- Embedded Floating-Point Round Interrupt284
- Partially Executed Instructions285
- Performance Monitor Interrupt285
- Interrupt Ordering and Masking287
- Guidelines for System Software288
- Exception Priorities289
- Interrupt Order289
- E500 Exception Priorities291
- E500 Interrupt Latency291
Mbar Instruction Timing Considerations219
- Memory Synchronization Timing Considerations219
Guarded Load and Cache-Inhibited Stwcx. Instructions292
Chapter 6 Power Management293
- Overview293
- Power Management Signals293
- Core and Integrated Device Power Management States294
- Core Power Management State Diagram294
- Power Management Control Bits295
- Software Considerations for Power Management296
- Power Management Protocol297
- Interrupts and Power Management298
Chapter 7 Performance Monitor299
- Overview299
- Performance Monitor APU Registers300
- Global Control Register 0 (PMGC0)302
  - User Performance Monitor Global Control Register 0 (UPMGC0)302
- User Global Control Register 0 (UPMGC0)303
- Local Control a Registers (Pmlca0-Pmlca3)303
- User Local Control a Registers (Upmlca0-Upmlca3)304
- Local Control B Registers (Pmlcb0-Pmlcb3)304
- User Local Control B Registers (Upmlcb0-Upmlcb3)305
- Performance Monitor Counter Registers (PMC0-PMC3)306
- User Performance Monitor Counter Registers (UPMC0-UPMC3)307
- Performance Monitor APU Instructions307
- Performance Monitor Interrupt308
- Event Counting308
- Processor Context Configurability308
- Examples309
- Chaining Counters309
- Thresholding310
- Event Selection310
Chapter 8 Debug Support317
- Overview317
- Programming Model317
- Register Set317
- Instruction Set318
- Debug Interrupt Model318
- Deviations from the Book E Debug Model319
- Hardware Facilities320
- TAP Controller and Register Model320
- TAP Interface Signals321
- Book E Debug Events322
- Instruction Address Compare Debug Event323
- Instruction Address Compare User and Supervisor Modes323
- Effective Address Mode324
- Instruction Address Compare Mode324
- Data Address Compare Debug Event325
- Data Address Compare Read/Write Enable325
- Data Address Compare User/Supervisor Mode326
- Effective Address Mode326
- Data Address Compare (DAC) Mode326
- Trap Debug Event327
- Branch Taken Debug Event328
- Instruction Complete Debug Event328
- Interrupt Taken Debug Event329
- Return Debug Event329
- Unconditional Debug Event330
E500 Core Complex331
Chapter 9 Timer Facilities333
- Timer Registers334
- The E500 Timer Implementation335
- Alternate Time Base APU336
- Performance Monitor Time Base Event336
Chapter 10 Auxiliary Processing Units (Apus)337
- Overview337
- Branch Target Buffer (BTB) Locking APU338
- BTB Locking APU Programming Model338
- BTB Locking APU Instructions338
- Vector and Floating-Point Apus338
- BTB Locking APU Registers339
- Alternate Time Base APU339
- Programming Model339
- Double-Precision Floating-Point APU (E500 V2 Only)340
- Programming Model340
- Double-Precision Floating-Point APU Operations340
- Operational Modes340
- Floating-Point Data Formats341
- Overflow and Underflow342
- Instruction Descriptions342
- Embedded Floating-Point Results Summary358
- Floating-Point Conversion Models358
- Common Functions358
- Convert from Double-Precision Floating-Point to Integer Word with Saturation359
- Convert to Double-Precision Floating-Point from Integer Word with Saturation361
Chapter 11363
- Overview363
- Block Diagram365
- Load/Store Unit (LSU)365
- Caching-Allowed Loads and the LSU366
- Store Queue366
- L1 Load Miss Queue (LMQ)366
- Data Line Fill Buffer (DLFB)366
- Data Write Buffer (DWB)367
- Instruction Unit367
- Core Interface Unit367
- L1 Cache Organization368
- L1 Data Cache Organization368
- L1 Instruction Cache Organization369
- L1 Cache Parity370
- Cache Parity Error Injection371
- Cache Coherency Support371
- Data Cache Coherency Model371
- Instruction Cache Coherency Model373
- Snoop Signaling374
- WIMGE Settings and Effect on L1 Caches375
- Write-Back Stores375
- Write-Through Stores375
- Caching-Inhibited Loads and Stores375
- Misaligned Accesses and the Endian (E) Bit375
- Speculative Accesses to Guarded Memory375
- Load/Store Operations376
- Performed Loads and Stores376
- Sequential Consistency of Memory Accesses377
- Enforcing Store Ordering with Respect to Loads377
- Atomic Memory References377
- L1 Cache Control378
- Cache Control Instructions378
- L1 Instruction and Data Cache Enabling/Disabling380
- L1 Instruction and Data Cache Flash Invalidation380
- L1 Instruction and Data Cache Line Locking/Unlocking381
- Effects of Other Cache Instructions on Locked Lines383
- Flash Clearing of Lock Bits383
- L1 Data Cache Flushing384
- L1 Cache Operation384
- Cache Miss and Reload Operations385
- Data Cache Fills385
- Instruction Cache Fills385
- Cache Allocation on Misses386
- Store Miss Merging386
- Store Hit to a Data Cache Block Marked Shared386
- Data Cache Block Push Operation386
- L1 Cache Block Replacement387
- PLRU Replacement387
- PLRU Bit Updates388
- Cache Locking and PLRU389
- L2 Cache Support389
- Invalidating the L2 Cache after a Cache Tag Parity Error389
- L2 Locking389
- L2 Unlocking390
- L1 Overlock390
Chapter 12 Memory Management Units391
- E500 MMU Overview391
- MMU Features391
- TLB Entry Maintenance Features393
- Effective-To-Real Address Translation394
- Virtual Addresses with Three PID Registers395
- Variable-Sized396
- Checking for TLB Entry Hit397
- Checking for Access Permissions397
- Translation Lookaside Buffers (Tlbs)398
- L1 TLB Arrays399
- L1 MMU TLB Organization400
- L2 TLB Arrays401
- IPROT Invalidation Protection in TLB1402
- Replacement Algorithms for L2 MMU403
- Round-Robin Replacement for TLB0-E500V1404
- Round Robin Replacement for TLB0-E500V1404
- Round-Robin Replacement for TLB0-E500V2404
- Round Robin Replacement for TLB0-E500V2404
- Consistency between L1 and L2 Tlbs405
- L1 and L2 TLB Access Times406
- The G Bit (of WIMGE)406
- TLB Entry Field Definitions407
- TLB Instructions-Implementation407
TLB Read Entry (Tlbre) Instruction408
- Reading Entries from the TLB1 Array408
- Reading Entries from the TLB0 Array408
TLB Write Entry (Tlbwe) Instruction409
- Writing to the TLB1 Array409
- Writing to the TLB0 Array409
TLB Search (Tlbsx) Instruction-Searching the TLB1 and TLB0 Arrays409
TLB Invalidate (Tlbivax) Instruction410
TLB Selection for Tlbivax Instruction411
Invalidate All Address Encoding for Tlbivax Instruction412
- TLB Invalidate Broadcast Enabling412
TLB Synchronize (Tlbsync) Instruction412
- TLB Entry Maintenance-Details412
- Automatic Updates-TLB Miss Exceptions413
- TLB Interrupt Routines414
- Permissions Violations (ISI, DSI) Interrupt Handlers414
- TLB States after Reset414
- Core Complex MMU Registers415
- E500 MAS Registers416
- MAS Register 1 (MAS1)417
- MAS Register 2 (MAS2)418
- MAS Register 3 (MAS3)419
- MAS Register 4 (MAS4)420
- MAS Register 7 (MAS7)421
- MAS Register Updates422
Chapter 13 Core Complex Bus (CCB)423
- Overview423
- Signal Summary424
- Core Interface Behavior427
- Parity Specification427
Msync Operation and the Bus428
Mbar Operation and the Bus428
- Address Streaming Mode429
- L2 Cache Support429
- L2 Locking429
- L2 Unlocking430
- L1 Overlock430
- Reservation Management430
- Remote Atomic Status Monitoring431
- Proper Reporting of Bus Faults431
Appendix A Programming Examples433
- Synchronization433
- A.1 Synchronization433
- Synchronization Primitives434
- Fetch and No-Op434
- A.1.1 Synchronization Primitives434
- Fetch and Store435
- Fetch and and435
- Notes436
- A.1.1.5 Test and Set436
- Lock Acquisition and Release437
- List Insertion438
- A.1.3 List Insertion438
- Notes439
- A.1.3.1 Notes439
Appendix B Guidelines for 32-Bit Book E441
- 64-Bit-Specific Book E Instructions441
- B.1 64-Bit–Specific Book E Instructions441
- Registers on 32-Bit Book E Implementations442
- Addressing on 32-Bit Book E Implementations442
- TLB Fields on 32-Bit Book E Implementations442
- 32-Bit Book E Software Guidelines443
- 32-Bit Instruction Selection443
- 32-Bit Addressing443
Appendix C Simplified Mnemonics for Powerpc Instructions445
- Overview445
- C.1 Overview445
- Subtract Simplified Mnemonics446
- Subtract Immediate446
- Subtract446
- Rotate and Shift Simplified Mnemonics446
- Operations on Words447
- C.3.1 Operations on Words447
- Branch Instruction Simplified Mnemonics448
- Key Facts about Simplified Branch Mnemonics449
- Eliminating the BO Operand449
- C-2 BO Field (Bits 6–10 of the Instruction Encoding)450
- Incorporating the BO Branch Prediction451
- The BI Operand-CR Bit and Field Representations452
- BI Operand Instruction Encoding452
- Specifying a CR Bit453
- BO Field (Bits 6-10 of the Instruction Encoding453
- C.4.4.1.1 Specifying a CR Bit453
- The Crs Operand454
- Simplified Mnemonics that Incorporate the BO Operand455
- Examples that Eliminate the BO Operand456
Simplified Mnemonics that Incorporate CR Conditions (Eliminates BO and Replaces BI with Crs459
- Branch Simplified Mnemonics that Incorporate CR Conditions: Examples461
- Compare Word Simplified Mnemonics464
- Condition Register Logical Simplified Mnemonics464
- Trap Instructions Simplified Mnemonics465
- Simplified Mnemonics for Accessing Sprs467
- Recommended Simplified Mnemonics468
No-Op (Nop468
Load Immediate (Li468
Load Address (la468
Move Register (Mr469
Complement Register (Not469
Move to Condition Register (Mtcr469
- EIS-Specific Simplified Mnemonics470
Integer Select (Isel470
- SPE Mnemonics470
Appendix D Opcode Listings481
- Instructions (Binary) by Mnemonic481
- Instructions (Decimal and Hexadecimal) by Opcode502
- Instructions by Form515
- D.3 Instructions by Form515
Appendix E Revision History531
- Major Changes from Revision 0 to Revision 1531
Chapter 3 Instruction Model532
Chapter 4 Execution Timing536
Chapter 5 Interrupts and Exceptions547
- Power Management548

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