Freescale Semiconductor PowerPC e500 Core - Page 241

Execution Timing
PowerPC e500 Core Family Reference Manual, Rev. 1
Freescale Semiconductor 4-39
efdnabs MU 6:1
efdneg MU 6:1
efdsub MU 6:1
efdtsteq MU 6:1
efdtstgt MU 6:1
efdtstlt MU 6:1
efsabs SU1 or SU2 1
efsadd MU 4:1
efscfsf MU 4:1
efscfsi MU 4:1
efscfuf MU 4:1
efscfui MU 4:1
efscmpeq SU1 4:1
efscmpgt SU1 1
efscmplt SU1 1
efsctsf MU 4:1
efsctsi MU 4:1
efsctsiz MU 4:1
efsctuf MU 4:1
efsctui MU 4:1
efsctuiz MU 4:1
efsdiv MU
1
4 (if either rA or rB is 0.0)
29 (all other cases)
efsmul MU 4:1
efsnabs SU1 or SU2 4:1
efsneg SU1 or SU2 1
efssub MU 4:1
efststeq SU1 or SU2 4:1
efststgt SU1 or SU2 1
efststlt SU1 or SU2 1
evabs SU1 1
evaddiw SU1 1
evaddsmiaaw MU 4:1
evaddssiaaw MU 4:1
evaddumiaaw MU 4:1
evaddusiaaw MU 4:1
evaddw SU1 1
evand SU1 1
Table 4-8. SPE and Embedded Floating-Point APU Instruction Latencies (continued)
Mnemonic Unit Cycles (Latency:Throughput)