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Ethernet (ETH): media access control (MAC) with DMA controller RM0008

1020/1096 Doc ID 13902 Rev 12

Ethernet MMC transmit interrupt register (ETH_MMCTIR)

Address offset: 0x0108

Reset value: 0x0000 0000

The Ethernet MMC transmit Interrupt register maintains the interrupts generated when

transmit statistic counters reach half their maximum values. (MSB of the counter is set.) It is

a 32-bit wide register. An interrupt bit is cleared when the respective MMC counter that

caused the interrupt is read. The least significant byte lane (bits [7:0]) of the respective

counter must be read in order to clear the interrupt bit.

Bits 16:7 Reserved

Bit 6 RFAES: Received frames alignment error status

This bit is set when the received frames, with alignment error, counter reaches half the

maximum value.

Bit 5 RFCES: Received frames CRC error status

This bit is set when the received frames, with CRC error, counter reaches half the maximum

value.

Bits 4:0 Reserved

313029282726252423222120191817161514131211109876543210

Reserved

TGFS

Reserved

TGFMSCS

TGFSCS

Reserved

rc_r rc_r rc_r

Bits 31:22 Reserved

Bit 21 TGFS: Transmitted good frames status

This bit is set when the transmitted, good frames, counter reaches half the maximum value.

Bits 20:16 Reserved

Bit 15 TGFMSCS: Transmitted good frames more single collision status

This bit is set when the transmitted, good frames after more than a single collision, counter

reaches half the maximum value.

Bit 14 TGFSCS: Transmitted good frames single collision status

This bit is set when the transmitted, good frames after a single collision, counter reaches half

the maximum value.

Bits 13:0 Reserved

ST STM32F101xx User Manual

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