RM0008 Flexible static memory controller (FSMC)
Doc ID 13902 Rev 12 501/1096
Mode A - SRAM/PSRAM (CRAM) OE toggling
Figure 189. ModeA read accesses
Table 109. FSMC_BTRx bit fields
Bit
number
Bit name Value to set
31-16 0x0000
15-8 DATAST
Duration of the second access phase (DATAST+1 HCLK cycles for
write accesses, DATAST+3 HCLK cycles for read accesses).
This value cannot be 0 (minimum is 1).
7-4 0x0
3-0 ADDSET Duration of the first access phase (ADDSET+1 HCLK cycles) .
A[25:0]
NOE
(ADDSET +1) (DATAST + 1)
Memory transaction
Data strobe
NEx
D[15:0]
HCLK cycles HCLK cycles
NWE
NBL[1:0]
data driven
by memory
ai14722c
High
2 HCLK
cycles
Data sampled
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