ST STM32F101xx User Manual

Revision history RM0008
1086/1096 Doc ID 13902 Rev 12
23-Dec-2008 7
Memory map figure removed from reference manual. Section 3.1: System architecture on
page 47 modified. Section 3.4: Boot configuration on page 60 modified. Exiting Sleep
mode on page 71 modified. Section 6.3.2: RTC calibration on page 80 updated. Wakeup
event management on page 198 updated.
Section 7.3: RCC registers on page 96 updated. Section 13.2: DMA main features on
page 263 updated.
Section 13.3.5: Error management modified. Figure 48: DMA block diagram in
connectivity line devices on page 264 modified. Section 13.3.4: Programmable data width,
data alignment and endians on page 268 added.
Bit definition modified in Section 13.4.5: DMA channel x peripheral address register
(DMA_CPARx) (x = 1..7), where x = channel number) on page 277 and Section 13.4.6:
DMA channel x memory address register (DMA_CMARx) (x = 1..7), where x = channel
number) on page 277.
Note added below Figure 82: PWM input mode timing and Figure 128: PWM input mode
timing.
FSMC_NWAIT signal direction corrected in Figure 185: FSMC block diagram on page 490.
Value to set modified for bit 6 in Table 113: FSMC_BCRx bit fields, Tab l e 1 16 :
FSMC_BCRx bit fields and Table 122: FSMC_BCRx bit fields. Table 129: 8-bit NAND
Flash, Table 130: 16-bit NAND Flash and Table 131: 16-bit PC Card modified. NWAIT and
INTR signals separated in Table 131: 16-bit PC Card. Note added in PWAITEN bit
definition in PC Card/NAND Flash control registers 2..4 (FSMC_PCR2..4) on page 535.
Bit definitions updated in FIFO status and interrupt register 2..4 (FSMC_SR2..4) on
page 536. Note modified in ADDHLD and ADDSET bit definitions in SRAM/NOR-Flash
chip-select timing registers 1..4 (FSMC_BTR1..4) on page 523. Bit 8 is reserved in PC
Card/NAND Flash control registers 2..4 (FSMC_PCR2..4) on page 535.
MEMWAIT[15:8] bit definition modified in Common memory space timing register 2..4
(FSMC_PMEM2..4) on page 537.
ATTWAIT[15:8] bit definition modified in Attribute memory space timing registers 2..4
(FSMC_PATT2..4) on page 538.
Section 21.6.5: NAND Flash pre-wait functionality on page 531 modified. Figure 204:
NAND/PC Card controller timing for common memory access modified.
Note added below Table 99: NOR/PSRAM bank selection on page 492.
32-bit external memory access removed from Table 100: External memory address on
page 493 and note added.
Caution: added to Section 21.6.1: External memory interface signals.
NIOS16 description modified in Table 131: 16-bit PC Card on page 528.
Register description modified in Attribute memory space timing registers 2..4
(FSMC_PATT2..4) on page 538.
Resetting the password on page 563 step 2 corrected.
write_data signal modified in Figure 204: NAND/PC Card controller timing for common
memory access.
bxCAN main features on page 630 modified.
Section 26.3.8: Packet error checking on page 745 modified.
Section 31.6.3: Cortex-M3 TAP modified.
DBG_TIMx_STOP positions modified in DBGMCU_CR on page 1069.
Small text changes.
Table 232. Document revision history (continued)
Date Revision Changes

ST STM32F101xx Specifications

General

Brand	ST
Model	STM32F101xx
Category	Microcontrollers
Language	English