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Flexible static memory controller (FSMC) RM0008

496/1096 Doc ID 13902 Rev 12

NOR-Flash memories are addressed in 16-bit words. The maximum capacity is 512 Mbit

(26 address lines).

PSRAM/SRAM

PSRAM memories are addressed in 16-bit words. The maximum capacity is 512 Mbit (26

address lines).

21.5.2 Supported memories and transactions

Table 107 below displays an example of the supported devices, access modes and

transactions when the memory data bus is 16-bit for NOR, PSRAM and SRAM.

Transactions not allowed (or not supported) by the FSMC in this example appear in gray.

NWE O Write enable

NL(=NADV) O

Latch enable (this signal is called address valid, NADV, by some NOR

Flash devices)

NWAIT I NOR Flash wait input signal to the FSMC

Table 106. Non muxed I/Os PSRAM/SRAM

FSMC signal name I/O Function

CLK O Clock (only for PSRAM synchronous burst)

A[25:0] O Address bus

D[15:0] I/O Data bidirectional bus

NE[x] O Chip select, x = 1..4 (called NCE by PSRAM (Cellular RAM i.e. CRAM))

NOE O Output enable

NWE O Write enable

NL(= NADV) O Address valid only for PSRAM input (memory signal name: NADV)

NWAIT I PSRAM wait input signal to the FSMC

NBL[1] O Upper byte enable (memory signal name: NUB)

NBL[0] O Lowed byte enable (memory signal name: NLB)

Table 105. Muxed I/O NOR Flash (continued)

FSMC signal name I/O Function

ST STM32F101xx User Manual

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