General-purpose timers (TIM9 to TIM14) RM0008
442/1096 Doc ID 13902 Rev 12
16.6 TIM10/11/13/14 registers
16.6.1 TIM10/11/13/14 control register 1 (TIMx_CR1)
Address offset: 0x00
Reset value: 0x0000
1514131211109876543210
Reserved
CKD[1:0] ARPE
Reserved
URS UDIS CEN
rw rw rw rw rw rw
Bits 15:10 Reserved, always read as 0.
Bits 9:8 CKD: Clock division
This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and
sampling clock used by the digital filters (ETR, TIx),
00: t
DTS
= t
CK_INT
01: t
DTS
= 2 × t
CK_INT
10: t
DTS
= 4 × t
CK_INT
11: Reserved
Bit 7 ARPE: Auto-reload preload enable
0: TIMx_ARR register is not buffered
1: TIMx_ARR register is buffered
Bits 6:3 Reserved, always read as 0.
Bit 2 URS: Update request source
This bit is set and cleared by software to select the update interrupt (UEV) sources.
0: Any of the following events generate an UEV if enabled:
– Counter overflow
– Setting the UG bit
1: Only counter overflow generates an UEV if enabled.
Bit 1 UDIS: Update disable
This bit is set and cleared by software to enable/disable update interrupt (UEV) event
generation.
0: UEV enabled. An UEV is generated by one of the following events:
– Counter overflow
– Setting the UG bit.
Buffered registers are then loaded with their preload values.
1: UEV disabled. No UEV is generated, shadow registers keep their value (ARR, PSC,
CCRx). The counter and the prescaler are reinitialized if the UG bit is set.
Bit 0 CEN: Counter enable
0: Counter disabled
1: Counter enabled
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