Serial peripheral interface (SPI) RM0008
674/1096 Doc ID 13902 Rev 12
25 Serial peripheral interface (SPI)
Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx
microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx
microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
High-density devices are STM32F101xx and STM32F103xx microcontrollers where the
Flash memory density ranges between 256 and 512 Kbytes.
XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the
Flash memory density ranges between 768 Kbytes and 1 Mbyte.
Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
25.1 SPI introduction
In high-density, XL-density and connectivity line devices, the SPI interface gives the
flexibility to get either the SPI protocol or the I
2
S audio protocol. By default, it is the SPI
function that is selected. It is possible to switch the interface from SPI to I
2
S by software.
In low- and medium-density devices, the I
2
S protocol is not available.
The serial peripheral interface (SPI) allows half/ full-duplex, synchronous, serial
communication with external devices. The interface can be configured as the master and in
this case it provides the communication clock (SCK) to the external slave device. The
interface is also capable of operating in multimaster configuration.
It may be used for a variety of purposes, including Simplex synchronous transfers on two
lines with a possible bidirectional data line or reliable communication using CRC checking.
I
2
S is also a synchronous, serial communication interface with a 3-pin protocol. It can
address four different audio standards including the I
2
S Phillips standard, the MSB- and
LSB-justified standards and the PCM standard. It can operate in slave or master mode with
half-duplex communication. Master clock may be provided by the interface to an external
slave component when the I
2
S is configured as the communication master.
Warning: Since some SPI3/I2S3 pins are shared with JTAG pins
(SPI3_NSS/I2S3_WS with JTDI and SPI3_SCK/I2S3_CK with
JTDO), they are not controlled by the IO controller and are
reserved for JTAG usage (after each Reset).
For this purpose, prior to configure the SPI3/I2S3 pins, the
user has to disable the JTAG and use the SWD interface
(when debugging the application), or disable both JTAG/SWD
interfaces (for standalone applications). For more
information on the configuration of JTAG/SWD interface pins,
please refer to Section 9.3.5: JTAG/SWD alternate function
remapping.
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