Window watchdog (WWDG) RM0008
486/1096 Doc ID 13902 Rev 12
20.6.2 Configuration register (WWDG_CFR)
Address offset: 0x04
Reset value: 0x7F
20.6.3 Status register (WWDG_SR)
Address offset: 0x08
Reset value: 0x00
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
EWI
WDGTB[1:0]
W[6:0]
rs rw rw
Bit 31:10 Reserved
Bit 9 EWI: Early wakeup interrupt
When set, an interrupt occurs whenever the counter reaches the value 40h. This interrupt is
only cleared by hardware after a reset.
Bits 8:7 WDGTB[1:0]: Timer base
The time base of the prescaler can be modified as follows:
00: CK Counter Clock (PCLK1 div 4096) div 1
01: CK Counter Clock (PCLK1 div 4096) div 2
10: CK Counter Clock (PCLK1 div 4096) div 4
11: CK Counter Clock (PCLK1 div 4096) div 8
Bits 6:0 W[6:0]: 7-bit window value
These bits contain the window value to be compared to the downcounter.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
EWIF
rc_w0
Bit 31:1Reserved
Bit 0 EWIF: Early wakeup interrupt flag
This bit is set by hardware when the counter has reached the value 40h. It must be cleared
by software by writing ‘0. A write of ‘1 has no effect. This bit is also set if the interrupt is not
enabled.
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