RM0008 Window watchdog (WWDG)
Doc ID 13902 Rev 12 485/1096
20.6 WWDG registers
Refer to Section 2.1 on page 46 for a list of abbreviations used in register descriptions.
The peripheral registers can be accessed by half-words (16-bit) or words (32-bit).
20.6.1 Control register (WWDG_CR)
Address offset: 0x00
Reset value: 0x7F
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
WDGA T[6:0]
rs rw
Bits 31:8 Reserved
Bit 7 WDGA: Activation bit
This bit is set by software and only cleared by hardware after a reset. When WDGA = 1, the
watchdog can generate a reset.
0: Watchdog disabled
1: Watchdog enabled
Bits 6:0 T[6:0]: 7-bit counter (MSB to LSB)
These bits contain the value of the watchdog counter. It is decremented every (4096 x
2
WDGTB
) PCLK1 cycles. A reset is produced when it rolls over from 40h to 3Fh (T6 becomes
cleared).
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