ST STM32F101xx User Manual

USB on-the-go full-speed (OTG_FS) RM0008
892/1096 Doc ID 13902 Rev 12
Refer to Table 3 on page 50 for the register boundary addresses.
28.17 OTG_FS programming model
28.17.1 Core initialization
The application must perform the core initialization sequence. If the cable is connected
during power-up, the current mode of operation bit in the OTG_FS_GINTSTS (CMOD bit in
OTG_FS_GINTSTS) reflects the mode. The OTG_FS controller enters host mode when an
“A” plug is connected or device mode when a “B” plug is connected.
0xB48
OTG_FS_DOEP
INT2
Reserved
Reserved
B2BSTUP
Reserved
OTEPDIS
STUP
Reserved
EPDISD
XFRC
Reset value 00000
0xB68
OTG_FS_DOEP
INT3
Reserved
Reserved
B2BSTUP
Reserved
OTEPDIS
STUP
Reserved
EPDISD
XFRC
Reset value 00000
0x910
OTG_FS_DIEP
TSIZ0
Reserved
PKTC
NT
Reserved
XFRSIZ
Reset value 00 0000000
0x930
OTG_FS_DIEP
TSIZ1
Reserved
MCNT PKTCNT XFRSIZ
Reset value 0000000000000000000000000000000
0x950
OTG_FS_DIEP
TSIZ2
Reserved
MCNT PKTCNT XFRSIZ
Reset value 0000000000000000000000000000000
0x970
OTG_FS_DIEP
TSIZ3
Reserved
MCNT PKTCNT XFRSIZ
Reset value 0000000000000000000000000000000
0xB10
OTG_FS_DOEP
TSIZ0
Reserved
STUP
CNT
Reserved
PKTCNT
Reserved
XFRSIZ
Reset value 00 0 0000000
0xB30
OTG_FS_DOEP
TSIZ1
Reserved
RXDPID/
STUPCNT
PKTCNT XFRSIZ
Reset value 0000000000000000000000000000000
0xB50
OTG_FS_DOEP
TSIZ2
Reserved
RXDPID/
STUPCNT
PKTCNT XFRSIZ
Reset value 0000000000000000000000000000000
0xB70
OTG_FS_DOEP
TSIZ3
Reserved
RXDPID/
STUPCNT
PKTCNT XFRSIZ
Reset value 0000000000000000000000000000000
0xE00
OTG_FS_PCG
CCTL
Reserved
PHYSUSP
Reserved
GATEHCLK
STPPCLK
Reset value
Table 204. OTG_FS register map and reset values (continued)
Offset Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9 8 7 6 5 4 3 2 1 0

ST STM32F101xx Specifications

General

Brand	ST
Model	STM32F101xx
Category	Microcontrollers
Language	English