RM0008 Ethernet (ETH): media access control (MAC) with DMA controller
Doc ID 13902 Rev 12 941/1096
29.3 Ethernet pins
Table 205 shows the MAC signals and the corresponding MII/RMII default or remapped
signals. It also indicates the pins onto which the signals are input or output, and the pin
configuration.
Table 205. Ethernet pin configuration
MAC signals MII default MII remap RMII default RMII remap Pin Pin configuration
ETH_MDC MDC - MDC - PC1
AF output push-pull high-
speed (50 MHz)
ETH_MII_TXD2 TXD2 - - - PC2
AF output push-pull high-
speed (50 MHz)
ETH_MII_TX_CLK TX_CLK - - - PC3 Floating input (reset state)
ETH_MII_CRS CRS - - - PA0 Floating input (reset state)
ETH_MII_RX_CLK
ETH_RMII_REF_CLK
RX_CLK - REF_CLK - PA1 Floating input (reset state)
ETH_MDIO MDIO - MDIO - PA2
AF output push-pull high-
speed (50 MHz)
ETH_MII_COL COL - - - PA3 Floating input (reset state)
ETH_MII_RX_DV
ETH_RMII_CRS_DV
RX_DV - CRS_DV - PA7 Floating input (reset state)
ETH_MII_RXD0
ETH_RMII_RXD0
RXD0 - RXD0 - PC4 Floating input (reset state)
ETH_MII_RXD1
ETH_RMII_RXD1
RXD1 - RXD1 - PC5 Floating input (reset state)
ETH_MII_RXD2 RXD2 - - - PB0 Floating input (reset state)
ETH_MII_RXD3 RXD3 - - - PB1 Floating input (reset state)
ETH_MII_RX_ER RX_ER - - - PB10 Floating input (reset state)
ETH_MII_TX_EN
ETH_RMII_TX_EN
TX_EN - TX_EN - PB11
AF output push-pull high-
speed (50 MHz)
ETH_MII_TXD0
ETH_RMII_TXD0
TXD0 - TXD0 - PB12
AF output push-pull high-
speed (50 MHz)
ETH_MII_TXD1
ETH_RMII_TXD1
TXD1 - TXD1 - PB13
AF output push-pull high-
speed (50 MHz)
ETH_PPS_OUT PPS_OUT - PPS_OUT - PB5
AF output push-pull high-
speed (50 MHz)
ETH_MII_TXD3 TXD3 - - - PB8
AF output push-pull high-
speed (50 MHz)
ETH_RMII_CRS_DV - RX_DV - CRS_DV PD8 Floating input (reset state)
ETH_MII_RXD0
ETH_RMII_RXD0
- RXD0 - RXD0 PD9 Floating input (reset state)
ETH_MII_RXD1
ETH_RMII_RXD1
- RXD1 - RXD1 PD10 Floating input (reset state)
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