ST STM32F101xx User Manual

RM0008 USB on-the-go full-speed (OTG_FS)
Doc ID 13902 Rev 12 831/1096
Power and clock gating CSR map
There is a single register for power and clock gating. It is available in both host and device
modes.
28.16.2 OTG_FS global registers
These registers are available in both host and device modes, and do not need to be
reprogrammed when switching between these modes.
Bit values in the register descriptions are expressed in binary unless otherwise specified.
OTG_FS control and status register (OTG_FS_GOTGCTL)
Address offset: 0x000
Reset value: 0x0000 0800
The OTG_FS_GOTGCTL register controls the behavior and reflects the status of the OTG
function of the core.
Table 201. Data FIFO (DFIFO) access register map
FIFO access register section Address range Access
Device IN Endpoint 0/Host OUT Channel 0: DFIFO Write Access
Device OUT Endpoint 0/Host IN Channel 0: DFIFO Read Access
0x1000–0x1FFC
w
r
Device IN Endpoint 1/Host OUT Channel 1: DFIFO Write Access
Device OUT Endpoint 1/Host IN Channel 1: DFIFO Read Access
0x2000–0x2FFC
w
r
... ... ...
Device IN Endpoint x
(1)
/Host OUT Channel x
(1)
: DFIFO Write Access
Device OUT Endpoint x
(1)
/Host IN Channel x
(1)
: DFIFO Read Access
1. Where x is 3 in device mode and 7 in host mode.
0xX000h–0xXFFCh
w
r
Table 202. Power and clock gating control and status registers
Register name Acronym Offset address: 0xE00–0xFFF
Power and clock gating control register PCGCR 0xE00-0xE04
Reserved 0xE05–0xFFF
313029282726252423222120191817161514131211109876543210
Reserved
BSVLD ASVLD
DBCT
CIDSTS
Reserved
DHNPEN
HSHNPEN
HNPRQ
HNGSCS
Reserved
SRQ
SRQSCS
rrrr rwrwrwr rwr
Bits 31:20 Reserved

ST STM32F101xx Specifications

General

Brand	ST
Model	STM32F101xx
Category	Microcontrollers
Language	English