ST STM32F101xx User Manual

Revision history RM0008
1080/1096 Doc ID 13902 Rev 12
19-Oct-2007
continued
1
continued
Figure 114: Counter timing diagram, internal clock divided by 1, TIMx_ARR=0x6 and
Figure 129: Output compare mode, toggle on OC1. modified. CKD definition modified in
Section 15.4.1: TIMx control register 1 (TIMx_CR1).
Bit 8 and Bit 9 added to Section 6.4.2: RTC clock calibration register (BKP_RTCCR).
it 15 and Bit 16 added to DBGMCU_CR on page 1069. Section 26.5: I2C debug mode on
page 747 added.
Stop and Standby modified in Table 11: Low-power mode summary.
Table 13: Sleep-on-exit modified. Debug mode on page 75 modified.
HSITRIM[4:0] bit description modified in Section 7.3.1: Clock control register (RCC_CR).
Note modified in MCO description in Section 7.3.2: Clock configuration register
(RCC_CFGR). RCC_CR row modified in RCC register map and reset values on page 119.
Bits 15:0 description modified in Section 9.2.6: Port bit reset register (GPIOx_BRR)
(x=A..G). Embedded boot loader on page 61 added.
Figure 13, Figure 15, Figure 16, Figure 17 and Figure 18 modified.
Section 3.3.3: Embedded Flash memory on page 54 modified.
REV_ID bit description added to DBGMCU_IDCODE on page 1055.
Reset value modified in Clock control register (RCC_CR) on page 96 and HSITRIM[4:0]
description modified.
Section 9.1.1 on page 156 modified. Bit definitions modified in Section 9.2: GPIO registers
on page 165. Wakeup latency description modified in Table 14: Stop mode.
Clock control register (RCC_CR) reset value modified.
Note added in ASOS and ASOE bit descriptions in 6.4.2 on page 81.
Section 31.16.2: Debug support for timers, watchdog, bxCAN and I2C modified. Table 231:
DBG register map and reset values updated.
Section 23.5.3: Buffer descriptor table clarified.
Center-aligned mode (up/down counting) on page 289 and Center-aligned mode (up/down
counting) on page 356 updated.
Figure 85: Center-aligned PWM waveforms (ARR=8) on page 304 and Figure 131:
Center-aligned PWM waveforms (ARR=8) on page 370 modified.
RSTCAL description modified in Section 11.12.3: ADC control register 2 (ADC_CR2).
Note changed below Table 96: Min/max IWDG timeout period at 740 kHz (LSI). Note
added below Figure 8: Clock tree.
ADC conversion time modified in
Section 11.2: ADC main features.
Auto-injection on page 212 updated.
Note added in Section 11.9.9: Combined injected simultaneous + interleaved. Note added
to Section 9.3.2: Using OSC_IN/OSC_OUT pins as GPIO ports PD0/PD1. Small text
changes. Internal LSI RC frequency changed from 32 to 40 kHz. Table 96: Min/max IWDG
timeout period at 740 kHz (LSI) updated. Option byte addresses corrected in Figure 2:
Memory map and Table 5: Flash module organization (medium-density devices).
Information block organization modified in Section 3.3.3: Embedded Flash memory.
External event that trigger ADC conversion is EXTI line instead of external interrupt (see
Section 11: Analog-to-digital converter (ADC)).
Appendix A: Important notes on page 500 added.
Table 232. Document revision history (continued)
Date Revision Changes

ST STM32F101xx Specifications

General

Brand	ST
Model	STM32F101xx
Category	Microcontrollers
Language	English