RM0008 Revision history
Doc ID 13902 Rev 12 1089/1096
04-Dec-2009
10
(to be
continued
on next
page)
References to the STM32F10xxx
Cortex-M3 programming manual (PM0056) made
throughout the document.
The GPIO, AFIO, EXTI, ADC, DAC, CAN, FSMC, SDIO, USB_OTG registers are accessed
by words (32 bits).
The PWR, BKP, USART, SPI, I2C, TIM1&8, TIMx, TIM6&7, WWDG, IWDG, USB, RTC
registers are accessed by words (32 bits) or by half-words (16 bits).
The DMA registers are accessed by byte (8 bits), by words (32 bits) or by half-words (16
bits).
Upper USB OTG FS boundary address corrected in Table 3: Register boundary
addresses.
Note 4 modified in Reading the Flash memory.
Section 8.2: Clocks updated. Figure 11: Clock tree modified. Exiting Standby mode
modified. Caution added to the HPRE bit description and bit 22 description modified in
Section 8.3.2: Clock configuration register (RCC_CFGR).
Section 8.1.2: Power reset and Section 7.1.2: Power reset modified, Figure 7: Simplified
diagram of the reset circuit and Figure 10: Simplified diagram of the reset circuit modified.
HSE frequency range corrected in Section 7.3: RCC registers.
“USB” table replaced by Table 30: OTG_FS pin configuration.
Address offsets corrected in Section 13.4: DMA registers.
Note added to Table 65: ADC pins and V
DDA
description modified.
Figure 179: RTC simplified block diagram modified.
Frequency changed in Table 96: Min/max IWDG timeout period at 740 kHz (LSI).
Text changes in Section 20.4: How to program the watchdog timeout.
FSMC_TCR changed to FSMC_BTR in Section 21: Flexible static memory controller
(FSMC).
Section 25: Serial peripheral interface (SPI) structure revised.
NSS description clarified in Section 25.3.1: General description.
Section 25.2.2: I2S features modified. Note added to Section 25.3.2: Configuring the SPI
in slave mode. Figure 239: Data clock timing diagram modified. Section 25.3.4:
Configuring the SPI for Simplex communication clarified. Section 25.3.5: Data
transmission and reception procedures added.
Section 25.3.6: CRC calculation clarified. Section 25.3.7: Status flags updated.
Section 25.3.8: Disabling the SPI updated. Section 25.3.9: SPI communication using DMA
(direct memory addressing) updated. Section 25.3.10: Error flags modified.
Section 25.4.3: Clock generator updated. Note added to bit 6 (SPE) in Section 25.5.1: SPI
control register 1 (SPI_CR1) (not used in I2S mode). Note removed from the descriptions
of bits 6 and 7 in Section 25.5.2: SPI control register 2 (SPI_CR2). Note added to bit 7
(BSY) in Section 25.5.3: SPI status register (SPI_SR).
Section 25.4.4: I2S master mode modified.
Closing the communication specified. Bus error (BERR) modified. CCR bit definition
modified in Section 26.6.8: Clock control register (I2C_CCR).
Bit 14 definition modified in Section 26.6.3: Own address register 1 (I2C_OAR1).
Note added to Table 195: USART interrupt requests. SCLK replaced by CK throughout
Section 27: Universal synchronous asynchronous receiver transmitter (USART).
Figure 280: TC/TXE behavior when transmitting clarified. Start bit detection modified.
Transmission using DMA updated. Figure 295: Transmission using DMA added.
Figure 296: Reception using DMA added.
Table 232. Document revision history (continued)
Date Revision Changes
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