RM0008 Ethernet (ETH): media access control (MAC) with DMA controller
Doc ID 13902 Rev 12 995/1096
Rx DMA descriptors
The descriptor structure consists of four 32-bit words (16 bytes). These are shown in
Figure 356. The bit descriptions of RDES0, RDES1, RDES2 and RDES3 are given below.
Figure 356. Rx DMA descriptor structure
● RDES0: Receive descriptor Word0
RDES0 contains the received frame status, the frame length and the descriptor
ownership information.
RDES 3
O
W
N
Status [30:0]
Reserved
[30:29]
Buffer 2 byte count
[28:16]
CTRL
[15:14]
Buffer 1 byte count
[12:0]
Buffer 1 address [31:0]
Buffer 2 address [31:0] or Next descriptor address [31:0]
RDES 0
RDES 1
RDES 2
31 0
ai15644
Res.
CT
RL
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OWN
AFM
FL
ES
DE
SAF
LE
OE
VLAN
FS
LS
IPHCE
LCO
FT
RWT
RE
DE
CE
PCE
rw
Bit 31 OWN: Own bit
When set, this bit indicates that the descriptor is owned by the DMA of the MAC Subsystem.
When this bit is reset, it indicates that the descriptor is owned by the Host. The DMA clears this bit
either when it completes the frame reception or when the buffers that are associated with this
descriptor are full.
Bit 30 AFM: Destination address filter fail
When set, this bit indicates a frame that failed the DA filter in the MAC Core.
Bits 29:16 FL: Frame length
These bits indicate the byte length of the received frame that was transferred to host memory
(including CRC). This field is valid only when last descriptor (RDES0[8]) is set and descriptor error
(RDES0[14]) is reset.
This field is valid when last descriptor (RDES0[8]) is set. When the last descriptor and error
summary bits are not set, this field indicates the accumulated number of bytes that have been
transferred for the current frame.
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