Serial peripheral interface (SPI) RM0008
676/1096 Doc ID 13902 Rev 12
25.2.2 I
2
S features
● Simplex communication (only transmitter or receiver)
● Master or slave operations
● 8-bit programmable linear prescaler to reach accurate audio sample frequencies (from
8 kHz to 96 kHz)
● Data format may be 16-bit, 24-bit or 32-bit
● Packet frame is fixed to 16-bit (16-bit data frame) or 32-bit (16-bit, 24-bit, 32-bit data
frame) by audio channel
● Programmable clock polarity (steady state)
● Underrun flag in slave transmission mode and Overrun flag in reception mode (master
and slave)
● 16-bit register for transmission and reception with one data register for both channel
sides
● Supported I
2
S protocols:
–I
2
S Phillips standard
– MSB-Justified standard (Left-Justified)
– LSB-Justified standard (Right-Justified)
– PCM standard (with short and long frame synchronization on 16-bit channel frame
or 16-bit data frame extended to 32-bit channel frame)
● Data direction is always MSB first
● DMA capability for transmission and reception (16-bit wide)
● Master clock may be output to drive an external audio component. Ratio is fixed at
256 × F
S
(where F
S
is the audio sampling frequency)
● In connectivity line devices, both I
2
S (I2S2 and I2S3) have a dedicated PLL (PLL3) to
generate an even more accurate clock.
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