RM0008 Inter-integrated circuit (I
2
C) interface
Doc ID 13902 Rev 12 729/1096
Figure 269. I
2
C block diagram
1. SMBA is an optional signal in SMBus mode. This signal is not applicable if SMBus is disabled.
26.3.2 I
2
C slave mode
By default the I
2
C interface operates in Slave mode. To switch from default Slave mode to
Master mode a Start condition generation is needed.
The peripheral input clock must be programmed in the I2C_CR2 register in order to
generate correct timings. The peripheral input clock frequency must be at least:
● 2 MHz in Standard mode
● 4 MHz in Fast mode
As soon as a start condition is detected, the address is received from the SDA line and sent
to the shift register. Then it is compared with the address of the interface (OAR1) and with
OAR2 (if ENDUAL=1) or the General Call address (if ENGC = 1).
Note: In 10-bit addressing mode, the comparison includes the header sequence (11110xx0),
where xx denotes the two most significant bits of the address.
Header or address not matched: the interface ignores it and waits for another Start
condition.
Header matched (10-bit mode only): the interface generates an acknowledge pulse if the
ACK bit is set and waits for the 8-bit slave address.
Data shift register
Comparator
Own address register
Clock control
Status registers
Control registers
Control
Clock
control
Data
control
SCL
logic
Dual address register
Data register
PEC register
Interrupts
PEC calculation
SMBA
SDA
Register (CCR)
(SR1&SR2)
(CR1&CR2)
DMA requests & ACK
ai17189
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