ST STM32F101xx User Manual

Revision history RM0008
1090/1096 Doc ID 13902 Rev 12
04-Dec-2009
10
continued
TXFELVL bit description modified in OTG_FS AHB configuration register
(OTG_FS_GAHBCFG).
NPTXFE bit description modified in OTG_FS core interrupt register (OTG_FS_GINTSTS).
NPTXFEM bit description modified in OTG_FS interrupt mask register
(OTG_FS_GINTMSK).
Figure 311: Transmit FIFO write task modified.
Bit 22 is reserved in OTG_FS interrupt mask register (OTG_FS_GINTMSK).
Bit 29 description modified in OTG device endpoint-x control register
(OTG_FS_DIEPCTLx) (x = 1..3, where x = Endpoint_number).
Bits 21:20 no longer reserved in OTG_FS Host channel-x characteristics register
(OTG_FS_HCCHARx) (x = 0..7, where x = Channel_number).
There are only 4 IN and OUT endpoints:
– Bit descriptions corrected in OTG_FS device all endpoints interrupt register
(OTG_FS_DAINT).
– Bits 15:0 description corrected in OTG_FS device IN endpoint FIFO empty interrupt
mask register: (OTG_FS_DIEPEMPMSK) (there are only 4 endpoints).
– Table 204: OTG_FS register map and reset values corrected
Note added to Section 29.4: Ethernet functional description: SMI, MII and RMII on
page 942.
Note added to Unicast destination address filter and Multicast destination address filter.
System consideration during power-down on page 972 updated.
Figure 325: ETH block diagram modified. CIC bit description modified in TDES0: Transmit
descriptor Word0 and TDES0: Transmit descriptor Word0: Transmit time stamp control and
status on page 967.
Ethernet MAC hash table high register (ETH_MACHTHR) description clarified.
Description of bits 6:2 modified in Ethernet DMA bus mode register (ETH_DMABMR).
Peripheral register access specified in Section 29.8: Ethernet register descriptions.
23-Apr-2010 11
XL-density devices added.
Flash access control register (FLASH_ACR) inserted.
External source (HSE bypass) and External source (HSE bypass) : maximum HSE
frequency modified.
HSEBYP bit description modified in Section 7.3.1: Clock control register (RCC_CR) and
Section 8.3.1: Clock control register (RCC_CR).
SPI3_REMAP definition modified in Section 9.4.2: AF remap and debug I/O configuration
register (AFIO_MAPR).
Figure 48: DMA block diagram in connectivity line devices modified.
Figure 85: Center-aligned PWM waveforms (ARR=8) modified.
OIS1N and OIS1 bit descriptions modified in Section 14.4.2: TIM1&TIM8 control register 2
(TIMx_CR2).
FSMC block diagram reinserted.
Figure 202: Synchronous multiplexed read mode - NOR, PSRAM (CRAM) modified.
FSMC_ECCR2 and FSMC_ECCR3 reset value modified in Table 135: FSMC register
map.
Updated I2C Master mode
Slave address transmission on page 733
Notes modified in the bit 5 descriptions in OTG_FS core interrupt register
(OTG_FS_GINTSTS) and OTG_FS interrupt mask register (OTG_FS_GINTMSK).
Transmission using DMA updated.
Table 232. Document revision history (continued)
Date Revision Changes

ST STM32F101xx Specifications

General

Brand	ST
Model	STM32F101xx
Category	Microcontrollers
Language	English