RM0008 Ethernet (ETH): media access control (MAC) with DMA controller
Doc ID 13902 Rev 12 945/1096
Figure 328. MDIO timing and frame structure - Read cycle
SMI clock selection
The MAC initiates the Management Write/Read operation. The SMI clock is a divided clock
whose source is the application clock (AHB clock). The divide factor depends on the clock
range setting in the MII Address register.
Table 207 shows how to set the clock ranges.
29.4.2 Media-independent interface: MII
The media-independent interface (MII) defines the interconnection between the MAC
sublayer and the PHY for data transfer at 10 Mbit/s and 100 Mbit/s.
Table 207. Clock range
Selection HCLK clock MDC clock
0000 60-72 MHz AHB clock / 42
0001 Reserved -
0010 20-35 MHz AHB clock / 16
0011 35-60 MHz AHB clock / 26
0100, 0101, 0110, 0111 Reserved -
MDC
MDIO
32 1's 0 1 1 0
A4 A3 A2 A1 A0 R4 R3 R2 R1 R0
D15 D14
D1 D0
Preamble
Start
of
frame
OP
code
PHY address Register address
Turn
around
data
Data to PHY
ai15627
Data from PHY
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