ST STM32F101xx User Manual

RM0008 Inter-integrated circuit (I
2
C) interface
Doc ID 13902 Rev 12 749/1096
26.6.2 Control register 2 (I2C_CR2)
Address offset: 0x04
Reset value: 0x0000
Bit 4 ENARP: ARP enable
0: ARP disable
1: ARP enable
SMBus Device default address recognized if SMBTYPE=0
SMBus Host address recognized if SMBTYPE=1
Bit 3 SMBTYPE: SMBus type
0: SMBus Device
1: SMBus Host
Bit 2 Reserved, forced by hardware to 0.
Bit 1 SMBUS: SMBus mode
0: I
2
C mode
1: SMBus mode
Bit 0 PE: Peripheral enable
0: Peripheral disable
1: Peripheral enable: the corresponding IOs are selected as alternate functions depending
on SMBus bit.
Note: If this bit is reset while a communication is on going, the peripheral is disabled at the
end of the current communication, when back to IDLE state.
All bit resets due to PE=0 occur at the end of the communication.
In master mode, this bit must not be reset before the end of the communication.
1514131211109876543210
Reserved
LAST
DMA
EN
ITBUF
EN
ITEVT
EN
ITERR
EN
Reserved
FREQ[5:0]
rw rw rw rw rw rw rw rw rw rw rw
Bits 15:13 Reserved, forced by hardware to 0.
Bit 12 LAST: DMA last transfer
0: Next DMA EOT is not the last transfer
1: Next DMA EOT is the last transfer
Note: This bit is used in master receiver mode to permit the generation of a NACK on the last
received data.
Bit 11 DMAEN: DMA requests enable
0: DMA requests disabled
1: DMA request enabled when TxE=1 or RxNE =1
Bit 10 ITBUFEN: Buffer interrupt enable
0: TxE = 1 or RxNE = 1 does not generate any interrupt.
1:TxE = 1 or RxNE = 1 generates Event Interrupt (whatever the state of DMAEN)

ST STM32F101xx Specifications

General

Brand	ST
Model	STM32F101xx
Category	Microcontrollers
Language	English